and remove the patches in the last round of releases.
gfs2-don-t-deref-jdesc-in-evict.patch
-x86-microcode-amd-load-late-on-both-threads-too.patch
x86-smp-use-dedicated-cache-line-for-mwait_play_dead.patch
video-imsttfb-check-for-ioremap-failures.patch
fbdev-imsttfb-fix-use-after-free-bug-in-imsttfb_probe.patch
tcp-annotate-data-races-around-tp-notsent_lowat.patch
tcp-annotate-data-races-around-fastopenq.max_qlen.patch
tracing-histograms-return-an-error-if-we-fail-to-add-histogram-to-hist_vars-list.patch
-x86-cpu-amd-move-the-errata-checking-functionality-up.patch
-x86-cpu-amd-add-a-zenbleed-fix.patch
media-atomisp-fix-variable-dereferenced-before-check-asd.patch
-x86-microcode-amd-load-late-on-both-threads-too.patch
x86-smp-use-dedicated-cache-line-for-mwait_play_dead.patch
can-isotp-isotp_sendmsg-fix-return-error-fix-on-tx-path.patch
video-imsttfb-check-for-ioremap-failures.patch
tracing-fix-memory-leak-of-iter-temp-when-reading-trace_pipe.patch
ftrace-store-the-order-of-pages-allocated-in-ftrace_page.patch
ftrace-fix-possible-warning-on-checking-all-pages-used-in-ftrace_process_locs.patch
-x86-cpu-amd-move-the-errata-checking-functionality-up.patch
-x86-cpu-amd-add-a-zenbleed-fix.patch
net-phy-prevent-stale-pointer-dereference-in-phy_ini.patch
jbd2-recheck-chechpointing-non-dirty-buffer.patch
tracing-histograms-return-an-error-if-we-fail-to-add-histogram-to-hist_vars-list.patch
-x86-cpu-amd-move-the-errata-checking-functionality-up.patch
-x86-cpu-amd-add-a-zenbleed-fix.patch
gfs2-don-t-deref-jdesc-in-evict.patch
-x86-microcode-amd-load-late-on-both-threads-too.patch
x86-smp-use-dedicated-cache-line-for-mwait_play_dead.patch
video-imsttfb-check-for-ioremap-failures.patch
fbdev-imsttfb-fix-use-after-free-bug-in-imsttfb_probe.patch
tcp-annotate-data-races-around-tp-notsent_lowat.patch
tcp-annotate-data-races-around-fastopenq.max_qlen.patch
tracing-histograms-return-an-error-if-we-fail-to-add-histogram-to-hist_vars-list.patch
-x86-cpu-amd-move-the-errata-checking-functionality-up.patch
-x86-cpu-amd-add-a-zenbleed-fix.patch
selftests-bpf-make-test_align-selftest-more-robust.patch
selftests-bpf-workaround-verification-failure-for-fexit_bpf2bpf-func_replace_return_code.patch
selftests-bpf-fix-sk_assign-on-s390x.patch
-x86-cpu-amd-move-the-errata-checking-functionality-up.patch
-x86-cpu-amd-add-a-zenbleed-fix.patch
drm-ttm-fix-bulk_move-corruption-when-adding-a-entry.patch
spi-dw-remove-misleading-comment-for-mount-evans-soc.patch
scsi-sg-don-t-grab-scsi-host-module-reference.patch
-x86-cpu-amd-move-the-errata-checking-functionality-up.patch
-x86-cpu-amd-add-a-zenbleed-fix.patch
+++ /dev/null
-From b2d362e150f1a48e95b4224e6ad860948f48c158 Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:41:28 +0200
-Subject: x86/cpu/amd: Add a Zenbleed fix
-
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-
-Upstream commit: 522b1d69219d8f083173819fde04f994aa051a98
-
-Add a fix for the Zen2 VZEROUPPER data corruption bug where under
-certain circumstances executing VZEROUPPER can cause register
-corruption or leak data.
-
-The optimal fix is through microcode but in the case the proper
-microcode revision has not been applied, enable a fallback fix using
-a chicken bit.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/include/asm/microcode.h | 1
- arch/x86/include/asm/microcode_amd.h | 2 +
- arch/x86/include/asm/msr-index.h | 1
- arch/x86/kernel/cpu/amd.c | 60 +++++++++++++++++++++++++++++++++++
- arch/x86/kernel/cpu/common.c | 2 +
- 5 files changed, 66 insertions(+)
-
---- a/arch/x86/include/asm/microcode.h
-+++ b/arch/x86/include/asm/microcode.h
-@@ -5,6 +5,7 @@
- #include <asm/cpu.h>
- #include <linux/earlycpio.h>
- #include <linux/initrd.h>
-+#include <asm/microcode_amd.h>
-
- struct ucode_patch {
- struct list_head plist;
---- a/arch/x86/include/asm/microcode_amd.h
-+++ b/arch/x86/include/asm/microcode_amd.h
-@@ -48,11 +48,13 @@ extern void __init load_ucode_amd_bsp(un
- extern void load_ucode_amd_ap(unsigned int family);
- extern int __init save_microcode_in_initrd_amd(unsigned int family);
- void reload_ucode_amd(unsigned int cpu);
-+extern void amd_check_microcode(void);
- #else
- static inline void __init load_ucode_amd_bsp(unsigned int family) {}
- static inline void load_ucode_amd_ap(unsigned int family) {}
- static inline int __init
- save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; }
- static inline void reload_ucode_amd(unsigned int cpu) {}
-+static inline void amd_check_microcode(void) {}
- #endif
- #endif /* _ASM_X86_MICROCODE_AMD_H */
---- a/arch/x86/include/asm/msr-index.h
-+++ b/arch/x86/include/asm/msr-index.h
-@@ -407,6 +407,7 @@
- #define MSR_AMD64_DE_CFG 0xc0011029
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
-+#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
-
- #define MSR_AMD64_BU_CFG2 0xc001102a
- #define MSR_AMD64_IBSFETCHCTL 0xc0011030
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -66,6 +66,11 @@ static const int amd_erratum_383[] =
- static const int amd_erratum_1054[] =
- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-
-+static const int amd_zenbleed[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
-+
- static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
- {
- int osvw_id = *erratum++;
-@@ -971,6 +976,47 @@ static void init_amd_zn(struct cpuinfo_x
- }
- }
-
-+static bool cpu_has_zenbleed_microcode(void)
-+{
-+ u32 good_rev = 0;
-+
-+ switch (boot_cpu_data.x86_model) {
-+ case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
-+ case 0x60 ... 0x67: good_rev = 0x0860010b; break;
-+ case 0x68 ... 0x6f: good_rev = 0x08608105; break;
-+ case 0x70 ... 0x7f: good_rev = 0x08701032; break;
-+ case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;
-+
-+ default:
-+ return false;
-+ break;
-+ }
-+
-+ if (boot_cpu_data.microcode < good_rev)
-+ return false;
-+
-+ return true;
-+}
-+
-+static void zenbleed_check(struct cpuinfo_x86 *c)
-+{
-+ if (!cpu_has_amd_erratum(c, amd_zenbleed))
-+ return;
-+
-+ if (cpu_has(c, X86_FEATURE_HYPERVISOR))
-+ return;
-+
-+ if (!cpu_has(c, X86_FEATURE_AVX))
-+ return;
-+
-+ if (!cpu_has_zenbleed_microcode()) {
-+ pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
-+ msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ } else {
-+ msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ }
-+}
-+
- static void init_amd(struct cpuinfo_x86 *c)
- {
- early_init_amd(c);
-@@ -1073,6 +1119,8 @@ static void init_amd(struct cpuinfo_x86
- msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
-
- check_null_seg_clears_base(c);
-+
-+ zenbleed_check(c);
- }
-
- #ifdef CONFIG_X86_32
-@@ -1186,3 +1234,15 @@ void set_dr_addr_mask(unsigned long mask
- break;
- }
- }
-+
-+static void zenbleed_check_cpu(void *unused)
-+{
-+ struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
-+
-+ zenbleed_check(c);
-+}
-+
-+void amd_check_microcode(void)
-+{
-+ on_each_cpu(zenbleed_check_cpu, NULL, 1);
-+}
---- a/arch/x86/kernel/cpu/common.c
-+++ b/arch/x86/kernel/cpu/common.c
-@@ -2077,6 +2077,8 @@ void microcode_check(void)
-
- perf_check_microcode();
-
-+ amd_check_microcode();
-+
- /* Reload CPUID max function as it might've changed. */
- info.cpuid_level = cpuid_eax(0);
-
+++ /dev/null
-From 334baad709246598bfd30587a0e98b0d90f3f596 Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:31:32 +0200
-Subject: x86/cpu/amd: Move the errata checking functionality up
-
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-
-Upstream commit: 8b6f687743dacce83dbb0c7cfacf88bab00f808a
-
-Avoid new and remove old forward declarations.
-
-No functional changes.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/kernel/cpu/amd.c | 139 ++++++++++++++++++++++------------------------
- 1 file changed, 67 insertions(+), 72 deletions(-)
-
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -23,11 +23,6 @@
-
- #include "cpu.h"
-
--static const int amd_erratum_383[];
--static const int amd_erratum_400[];
--static const int amd_erratum_1054[];
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
--
- /*
- * nodes_per_socket: Stores the number of nodes per socket.
- * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
-@@ -35,6 +30,73 @@ static bool cpu_has_amd_erratum(struct c
- */
- static u32 nodes_per_socket = 1;
-
-+/*
-+ * AMD errata checking
-+ *
-+ * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-+ * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-+ * have an OSVW id assigned, which it takes as first argument. Both take a
-+ * variable number of family-specific model-stepping ranges created by
-+ * AMD_MODEL_RANGE().
-+ *
-+ * Example:
-+ *
-+ * const int amd_erratum_319[] =
-+ * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-+ * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-+ * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-+ */
-+
-+#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
-+#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
-+#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-+ ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
-+#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
-+#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
-+#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
-+
-+static const int amd_erratum_400[] =
-+ AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-+ AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
-+
-+static const int amd_erratum_383[] =
-+ AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
-+
-+/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
-+static const int amd_erratum_1054[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-+
-+static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
-+{
-+ int osvw_id = *erratum++;
-+ u32 range;
-+ u32 ms;
-+
-+ if (osvw_id >= 0 && osvw_id < 65536 &&
-+ cpu_has(cpu, X86_FEATURE_OSVW)) {
-+ u64 osvw_len;
-+
-+ rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-+ if (osvw_id < osvw_len) {
-+ u64 osvw_bits;
-+
-+ rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-+ osvw_bits);
-+ return osvw_bits & (1ULL << (osvw_id & 0x3f));
-+ }
-+ }
-+
-+ /* OSVW unavailable or ID unknown, match family-model-stepping range */
-+ ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-+ while ((range = *erratum++))
-+ if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-+ (ms >= AMD_MODEL_RANGE_START(range)) &&
-+ (ms <= AMD_MODEL_RANGE_END(range)))
-+ return true;
-+
-+ return false;
-+}
-+
- static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
- {
- u32 gprs[8] = { 0 };
-@@ -1106,73 +1168,6 @@ static const struct cpu_dev amd_cpu_dev
-
- cpu_dev_register(amd_cpu_dev);
-
--/*
-- * AMD errata checking
-- *
-- * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-- * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-- * have an OSVW id assigned, which it takes as first argument. Both take a
-- * variable number of family-specific model-stepping ranges created by
-- * AMD_MODEL_RANGE().
-- *
-- * Example:
-- *
-- * const int amd_erratum_319[] =
-- * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-- * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-- * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-- */
--
--#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
--#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
--#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-- ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
--#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
--#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
--#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
--
--static const int amd_erratum_400[] =
-- AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-- AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
--
--static const int amd_erratum_383[] =
-- AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
--
--/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
--static const int amd_erratum_1054[] =
-- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
--
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
--{
-- int osvw_id = *erratum++;
-- u32 range;
-- u32 ms;
--
-- if (osvw_id >= 0 && osvw_id < 65536 &&
-- cpu_has(cpu, X86_FEATURE_OSVW)) {
-- u64 osvw_len;
--
-- rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-- if (osvw_id < osvw_len) {
-- u64 osvw_bits;
--
-- rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-- osvw_bits);
-- return osvw_bits & (1ULL << (osvw_id & 0x3f));
-- }
-- }
--
-- /* OSVW unavailable or ID unknown, match family-model-stepping range */
-- ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-- while ((range = *erratum++))
-- if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-- (ms >= AMD_MODEL_RANGE_START(range)) &&
-- (ms <= AMD_MODEL_RANGE_END(range)))
-- return true;
--
-- return false;
--}
--
- void set_dr_addr_mask(unsigned long mask, int dr)
- {
- if (!boot_cpu_has(X86_FEATURE_BPEXT))
+++ /dev/null
-From a32b0f0db3f396f1c9be2fe621e77c09ec3d8e7d Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Tue, 2 May 2023 19:53:50 +0200
-Subject: x86/microcode/AMD: Load late on both threads too
-
-From: Borislav Petkov (AMD) <bp@alien8.de>
-
-commit a32b0f0db3f396f1c9be2fe621e77c09ec3d8e7d upstream.
-
-Do the same as early loading - load on both threads.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Cc: <stable@kernel.org>
-Link: https://lore.kernel.org/r/20230605141332.25948-1-bp@alien8.de
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/kernel/cpu/microcode/amd.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/x86/kernel/cpu/microcode/amd.c
-+++ b/arch/x86/kernel/cpu/microcode/amd.c
-@@ -532,7 +532,7 @@ static enum ucode_state apply_microcode_
- rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
-
- /* need to apply patch? */
-- if (rev >= mc_amd->hdr.patch_id) {
-+ if (rev > mc_amd->hdr.patch_id) {
- ret = UCODE_OK;
- goto out;
- }
+++ /dev/null
-From b2d362e150f1a48e95b4224e6ad860948f48c158 Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:41:28 +0200
-Subject: x86/cpu/amd: Add a Zenbleed fix
-
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-
-Upstream commit: 522b1d69219d8f083173819fde04f994aa051a98
-
-Add a fix for the Zen2 VZEROUPPER data corruption bug where under
-certain circumstances executing VZEROUPPER can cause register
-corruption or leak data.
-
-The optimal fix is through microcode but in the case the proper
-microcode revision has not been applied, enable a fallback fix using
-a chicken bit.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/include/asm/microcode.h | 1
- arch/x86/include/asm/microcode_amd.h | 2 +
- arch/x86/include/asm/msr-index.h | 1
- arch/x86/kernel/cpu/amd.c | 60 +++++++++++++++++++++++++++++++++++
- arch/x86/kernel/cpu/common.c | 2 +
- 5 files changed, 66 insertions(+)
-
---- a/arch/x86/include/asm/microcode.h
-+++ b/arch/x86/include/asm/microcode.h
-@@ -5,6 +5,7 @@
- #include <asm/cpu.h>
- #include <linux/earlycpio.h>
- #include <linux/initrd.h>
-+#include <asm/microcode_amd.h>
-
- struct ucode_patch {
- struct list_head plist;
---- a/arch/x86/include/asm/microcode_amd.h
-+++ b/arch/x86/include/asm/microcode_amd.h
-@@ -48,11 +48,13 @@ extern void __init load_ucode_amd_bsp(un
- extern void load_ucode_amd_ap(unsigned int family);
- extern int __init save_microcode_in_initrd_amd(unsigned int family);
- void reload_ucode_amd(unsigned int cpu);
-+extern void amd_check_microcode(void);
- #else
- static inline void __init load_ucode_amd_bsp(unsigned int family) {}
- static inline void load_ucode_amd_ap(unsigned int family) {}
- static inline int __init
- save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; }
- static inline void reload_ucode_amd(unsigned int cpu) {}
-+static inline void amd_check_microcode(void) {}
- #endif
- #endif /* _ASM_X86_MICROCODE_AMD_H */
---- a/arch/x86/include/asm/msr-index.h
-+++ b/arch/x86/include/asm/msr-index.h
-@@ -497,6 +497,7 @@
- #define MSR_AMD64_DE_CFG 0xc0011029
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
-+#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
-
- #define MSR_AMD64_BU_CFG2 0xc001102a
- #define MSR_AMD64_IBSFETCHCTL 0xc0011030
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -71,6 +71,11 @@ static const int amd_erratum_383[] =
- static const int amd_erratum_1054[] =
- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-
-+static const int amd_zenbleed[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
-+
- static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
- {
- int osvw_id = *erratum++;
-@@ -1030,6 +1035,47 @@ static void init_amd_zn(struct cpuinfo_x
- }
- }
-
-+static bool cpu_has_zenbleed_microcode(void)
-+{
-+ u32 good_rev = 0;
-+
-+ switch (boot_cpu_data.x86_model) {
-+ case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
-+ case 0x60 ... 0x67: good_rev = 0x0860010b; break;
-+ case 0x68 ... 0x6f: good_rev = 0x08608105; break;
-+ case 0x70 ... 0x7f: good_rev = 0x08701032; break;
-+ case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;
-+
-+ default:
-+ return false;
-+ break;
-+ }
-+
-+ if (boot_cpu_data.microcode < good_rev)
-+ return false;
-+
-+ return true;
-+}
-+
-+static void zenbleed_check(struct cpuinfo_x86 *c)
-+{
-+ if (!cpu_has_amd_erratum(c, amd_zenbleed))
-+ return;
-+
-+ if (cpu_has(c, X86_FEATURE_HYPERVISOR))
-+ return;
-+
-+ if (!cpu_has(c, X86_FEATURE_AVX))
-+ return;
-+
-+ if (!cpu_has_zenbleed_microcode()) {
-+ pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
-+ msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ } else {
-+ msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ }
-+}
-+
- static void init_amd(struct cpuinfo_x86 *c)
- {
- early_init_amd(c);
-@@ -1120,6 +1166,8 @@ static void init_amd(struct cpuinfo_x86
- msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
-
- check_null_seg_clears_base(c);
-+
-+ zenbleed_check(c);
- }
-
- #ifdef CONFIG_X86_32
-@@ -1233,3 +1281,15 @@ void set_dr_addr_mask(unsigned long mask
- break;
- }
- }
-+
-+static void zenbleed_check_cpu(void *unused)
-+{
-+ struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
-+
-+ zenbleed_check(c);
-+}
-+
-+void amd_check_microcode(void)
-+{
-+ on_each_cpu(zenbleed_check_cpu, NULL, 1);
-+}
---- a/arch/x86/kernel/cpu/common.c
-+++ b/arch/x86/kernel/cpu/common.c
-@@ -2165,6 +2165,8 @@ void microcode_check(struct cpuinfo_x86
-
- perf_check_microcode();
-
-+ amd_check_microcode();
-+
- store_cpu_caps(&curr_info);
-
- if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
+++ /dev/null
-From 334baad709246598bfd30587a0e98b0d90f3f596 Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:31:32 +0200
-Subject: x86/cpu/amd: Move the errata checking functionality up
-
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-
-Upstream commit: 8b6f687743dacce83dbb0c7cfacf88bab00f808a
-
-Avoid new and remove old forward declarations.
-
-No functional changes.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/kernel/cpu/amd.c | 139 ++++++++++++++++++++++------------------------
- 1 file changed, 67 insertions(+), 72 deletions(-)
-
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -28,11 +28,6 @@
-
- #include "cpu.h"
-
--static const int amd_erratum_383[];
--static const int amd_erratum_400[];
--static const int amd_erratum_1054[];
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
--
- /*
- * nodes_per_socket: Stores the number of nodes per socket.
- * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
-@@ -40,6 +35,73 @@ static bool cpu_has_amd_erratum(struct c
- */
- static u32 nodes_per_socket = 1;
-
-+/*
-+ * AMD errata checking
-+ *
-+ * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-+ * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-+ * have an OSVW id assigned, which it takes as first argument. Both take a
-+ * variable number of family-specific model-stepping ranges created by
-+ * AMD_MODEL_RANGE().
-+ *
-+ * Example:
-+ *
-+ * const int amd_erratum_319[] =
-+ * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-+ * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-+ * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-+ */
-+
-+#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
-+#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
-+#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-+ ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
-+#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
-+#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
-+#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
-+
-+static const int amd_erratum_400[] =
-+ AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-+ AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
-+
-+static const int amd_erratum_383[] =
-+ AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
-+
-+/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
-+static const int amd_erratum_1054[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-+
-+static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
-+{
-+ int osvw_id = *erratum++;
-+ u32 range;
-+ u32 ms;
-+
-+ if (osvw_id >= 0 && osvw_id < 65536 &&
-+ cpu_has(cpu, X86_FEATURE_OSVW)) {
-+ u64 osvw_len;
-+
-+ rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-+ if (osvw_id < osvw_len) {
-+ u64 osvw_bits;
-+
-+ rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-+ osvw_bits);
-+ return osvw_bits & (1ULL << (osvw_id & 0x3f));
-+ }
-+ }
-+
-+ /* OSVW unavailable or ID unknown, match family-model-stepping range */
-+ ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-+ while ((range = *erratum++))
-+ if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-+ (ms >= AMD_MODEL_RANGE_START(range)) &&
-+ (ms <= AMD_MODEL_RANGE_END(range)))
-+ return true;
-+
-+ return false;
-+}
-+
- static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
- {
- u32 gprs[8] = { 0 };
-@@ -1153,73 +1215,6 @@ static const struct cpu_dev amd_cpu_dev
-
- cpu_dev_register(amd_cpu_dev);
-
--/*
-- * AMD errata checking
-- *
-- * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-- * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-- * have an OSVW id assigned, which it takes as first argument. Both take a
-- * variable number of family-specific model-stepping ranges created by
-- * AMD_MODEL_RANGE().
-- *
-- * Example:
-- *
-- * const int amd_erratum_319[] =
-- * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-- * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-- * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-- */
--
--#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
--#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
--#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-- ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
--#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
--#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
--#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
--
--static const int amd_erratum_400[] =
-- AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-- AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
--
--static const int amd_erratum_383[] =
-- AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
--
--/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
--static const int amd_erratum_1054[] =
-- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
--
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
--{
-- int osvw_id = *erratum++;
-- u32 range;
-- u32 ms;
--
-- if (osvw_id >= 0 && osvw_id < 65536 &&
-- cpu_has(cpu, X86_FEATURE_OSVW)) {
-- u64 osvw_len;
--
-- rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-- if (osvw_id < osvw_len) {
-- u64 osvw_bits;
--
-- rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-- osvw_bits);
-- return osvw_bits & (1ULL << (osvw_id & 0x3f));
-- }
-- }
--
-- /* OSVW unavailable or ID unknown, match family-model-stepping range */
-- ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-- while ((range = *erratum++))
-- if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-- (ms >= AMD_MODEL_RANGE_START(range)) &&
-- (ms <= AMD_MODEL_RANGE_END(range)))
-- return true;
--
-- return false;
--}
--
- void set_dr_addr_mask(unsigned long mask, int dr)
- {
- if (!boot_cpu_has(X86_FEATURE_BPEXT))
+++ /dev/null
-From a32b0f0db3f396f1c9be2fe621e77c09ec3d8e7d Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Tue, 2 May 2023 19:53:50 +0200
-Subject: x86/microcode/AMD: Load late on both threads too
-
-From: Borislav Petkov (AMD) <bp@alien8.de>
-
-commit a32b0f0db3f396f1c9be2fe621e77c09ec3d8e7d upstream.
-
-Do the same as early loading - load on both threads.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Cc: <stable@kernel.org>
-Link: https://lore.kernel.org/r/20230605141332.25948-1-bp@alien8.de
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/kernel/cpu/microcode/amd.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/x86/kernel/cpu/microcode/amd.c
-+++ b/arch/x86/kernel/cpu/microcode/amd.c
-@@ -700,7 +700,7 @@ static enum ucode_state apply_microcode_
- rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
-
- /* need to apply patch? */
-- if (rev >= mc_amd->hdr.patch_id) {
-+ if (rev > mc_amd->hdr.patch_id) {
- ret = UCODE_OK;
- goto out;
- }
+++ /dev/null
-From b2d362e150f1a48e95b4224e6ad860948f48c158 Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:41:28 +0200
-Subject: x86/cpu/amd: Add a Zenbleed fix
-
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-
-Upstream commit: 522b1d69219d8f083173819fde04f994aa051a98
-
-Add a fix for the Zen2 VZEROUPPER data corruption bug where under
-certain circumstances executing VZEROUPPER can cause register
-corruption or leak data.
-
-The optimal fix is through microcode but in the case the proper
-microcode revision has not been applied, enable a fallback fix using
-a chicken bit.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/include/asm/microcode.h | 1
- arch/x86/include/asm/microcode_amd.h | 2 +
- arch/x86/include/asm/msr-index.h | 1
- arch/x86/kernel/cpu/amd.c | 60 +++++++++++++++++++++++++++++++++++
- arch/x86/kernel/cpu/common.c | 2 +
- 5 files changed, 66 insertions(+)
-
---- a/arch/x86/include/asm/microcode.h
-+++ b/arch/x86/include/asm/microcode.h
-@@ -5,6 +5,7 @@
- #include <asm/cpu.h>
- #include <linux/earlycpio.h>
- #include <linux/initrd.h>
-+#include <asm/microcode_amd.h>
-
- struct ucode_patch {
- struct list_head plist;
---- a/arch/x86/include/asm/microcode_amd.h
-+++ b/arch/x86/include/asm/microcode_amd.h
-@@ -48,11 +48,13 @@ extern void __init load_ucode_amd_bsp(un
- extern void load_ucode_amd_ap(unsigned int family);
- extern int __init save_microcode_in_initrd_amd(unsigned int family);
- void reload_ucode_amd(unsigned int cpu);
-+extern void amd_check_microcode(void);
- #else
- static inline void __init load_ucode_amd_bsp(unsigned int family) {}
- static inline void load_ucode_amd_ap(unsigned int family) {}
- static inline int __init
- save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; }
- static inline void reload_ucode_amd(unsigned int cpu) {}
-+static inline void amd_check_microcode(void) {}
- #endif
- #endif /* _ASM_X86_MICROCODE_AMD_H */
---- a/arch/x86/include/asm/msr-index.h
-+++ b/arch/x86/include/asm/msr-index.h
-@@ -503,6 +503,7 @@
- #define MSR_AMD64_DE_CFG 0xc0011029
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
-+#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
-
- #define MSR_AMD64_BU_CFG2 0xc001102a
- #define MSR_AMD64_IBSFETCHCTL 0xc0011030
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -70,6 +70,11 @@ static const int amd_erratum_383[] =
- static const int amd_erratum_1054[] =
- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-
-+static const int amd_zenbleed[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
-+
- static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
- {
- int osvw_id = *erratum++;
-@@ -1002,6 +1007,47 @@ static void init_amd_zn(struct cpuinfo_x
- }
- }
-
-+static bool cpu_has_zenbleed_microcode(void)
-+{
-+ u32 good_rev = 0;
-+
-+ switch (boot_cpu_data.x86_model) {
-+ case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
-+ case 0x60 ... 0x67: good_rev = 0x0860010b; break;
-+ case 0x68 ... 0x6f: good_rev = 0x08608105; break;
-+ case 0x70 ... 0x7f: good_rev = 0x08701032; break;
-+ case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;
-+
-+ default:
-+ return false;
-+ break;
-+ }
-+
-+ if (boot_cpu_data.microcode < good_rev)
-+ return false;
-+
-+ return true;
-+}
-+
-+static void zenbleed_check(struct cpuinfo_x86 *c)
-+{
-+ if (!cpu_has_amd_erratum(c, amd_zenbleed))
-+ return;
-+
-+ if (cpu_has(c, X86_FEATURE_HYPERVISOR))
-+ return;
-+
-+ if (!cpu_has(c, X86_FEATURE_AVX))
-+ return;
-+
-+ if (!cpu_has_zenbleed_microcode()) {
-+ pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
-+ msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ } else {
-+ msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ }
-+}
-+
- static void init_amd(struct cpuinfo_x86 *c)
- {
- early_init_amd(c);
-@@ -1092,6 +1138,8 @@ static void init_amd(struct cpuinfo_x86
- msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
-
- check_null_seg_clears_base(c);
-+
-+ zenbleed_check(c);
- }
-
- #ifdef CONFIG_X86_32
-@@ -1221,3 +1269,15 @@ u32 amd_get_highest_perf(void)
- return 255;
- }
- EXPORT_SYMBOL_GPL(amd_get_highest_perf);
-+
-+static void zenbleed_check_cpu(void *unused)
-+{
-+ struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
-+
-+ zenbleed_check(c);
-+}
-+
-+void amd_check_microcode(void)
-+{
-+ on_each_cpu(zenbleed_check_cpu, NULL, 1);
-+}
---- a/arch/x86/kernel/cpu/common.c
-+++ b/arch/x86/kernel/cpu/common.c
-@@ -2185,6 +2185,8 @@ void microcode_check(struct cpuinfo_x86
-
- perf_check_microcode();
-
-+ amd_check_microcode();
-+
- store_cpu_caps(&curr_info);
-
- if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
+++ /dev/null
-From 334baad709246598bfd30587a0e98b0d90f3f596 Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:31:32 +0200
-Subject: x86/cpu/amd: Move the errata checking functionality up
-
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-
-Upstream commit: 8b6f687743dacce83dbb0c7cfacf88bab00f808a
-
-Avoid new and remove old forward declarations.
-
-No functional changes.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/kernel/cpu/amd.c | 139 ++++++++++++++++++++++------------------------
- 1 file changed, 67 insertions(+), 72 deletions(-)
-
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -27,11 +27,6 @@
-
- #include "cpu.h"
-
--static const int amd_erratum_383[];
--static const int amd_erratum_400[];
--static const int amd_erratum_1054[];
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
--
- /*
- * nodes_per_socket: Stores the number of nodes per socket.
- * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
-@@ -39,6 +34,73 @@ static bool cpu_has_amd_erratum(struct c
- */
- static u32 nodes_per_socket = 1;
-
-+/*
-+ * AMD errata checking
-+ *
-+ * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-+ * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-+ * have an OSVW id assigned, which it takes as first argument. Both take a
-+ * variable number of family-specific model-stepping ranges created by
-+ * AMD_MODEL_RANGE().
-+ *
-+ * Example:
-+ *
-+ * const int amd_erratum_319[] =
-+ * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-+ * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-+ * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-+ */
-+
-+#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
-+#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
-+#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-+ ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
-+#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
-+#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
-+#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
-+
-+static const int amd_erratum_400[] =
-+ AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-+ AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
-+
-+static const int amd_erratum_383[] =
-+ AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
-+
-+/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
-+static const int amd_erratum_1054[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-+
-+static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
-+{
-+ int osvw_id = *erratum++;
-+ u32 range;
-+ u32 ms;
-+
-+ if (osvw_id >= 0 && osvw_id < 65536 &&
-+ cpu_has(cpu, X86_FEATURE_OSVW)) {
-+ u64 osvw_len;
-+
-+ rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-+ if (osvw_id < osvw_len) {
-+ u64 osvw_bits;
-+
-+ rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-+ osvw_bits);
-+ return osvw_bits & (1ULL << (osvw_id & 0x3f));
-+ }
-+ }
-+
-+ /* OSVW unavailable or ID unknown, match family-model-stepping range */
-+ ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-+ while ((range = *erratum++))
-+ if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-+ (ms >= AMD_MODEL_RANGE_START(range)) &&
-+ (ms <= AMD_MODEL_RANGE_END(range)))
-+ return true;
-+
-+ return false;
-+}
-+
- static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
- {
- u32 gprs[8] = { 0 };
-@@ -1125,73 +1187,6 @@ static const struct cpu_dev amd_cpu_dev
-
- cpu_dev_register(amd_cpu_dev);
-
--/*
-- * AMD errata checking
-- *
-- * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-- * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-- * have an OSVW id assigned, which it takes as first argument. Both take a
-- * variable number of family-specific model-stepping ranges created by
-- * AMD_MODEL_RANGE().
-- *
-- * Example:
-- *
-- * const int amd_erratum_319[] =
-- * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-- * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-- * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-- */
--
--#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
--#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
--#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-- ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
--#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
--#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
--#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
--
--static const int amd_erratum_400[] =
-- AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-- AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
--
--static const int amd_erratum_383[] =
-- AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
--
--/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
--static const int amd_erratum_1054[] =
-- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
--
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
--{
-- int osvw_id = *erratum++;
-- u32 range;
-- u32 ms;
--
-- if (osvw_id >= 0 && osvw_id < 65536 &&
-- cpu_has(cpu, X86_FEATURE_OSVW)) {
-- u64 osvw_len;
--
-- rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-- if (osvw_id < osvw_len) {
-- u64 osvw_bits;
--
-- rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-- osvw_bits);
-- return osvw_bits & (1ULL << (osvw_id & 0x3f));
-- }
-- }
--
-- /* OSVW unavailable or ID unknown, match family-model-stepping range */
-- ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-- while ((range = *erratum++))
-- if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-- (ms >= AMD_MODEL_RANGE_START(range)) &&
-- (ms <= AMD_MODEL_RANGE_END(range)))
-- return true;
--
-- return false;
--}
--
- void set_dr_addr_mask(unsigned long mask, int dr)
- {
- if (!boot_cpu_has(X86_FEATURE_BPEXT))
+++ /dev/null
-From b2d362e150f1a48e95b4224e6ad860948f48c158 Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:41:28 +0200
-Subject: x86/cpu/amd: Add a Zenbleed fix
-
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-
-Upstream commit: 522b1d69219d8f083173819fde04f994aa051a98
-
-Add a fix for the Zen2 VZEROUPPER data corruption bug where under
-certain circumstances executing VZEROUPPER can cause register
-corruption or leak data.
-
-The optimal fix is through microcode but in the case the proper
-microcode revision has not been applied, enable a fallback fix using
-a chicken bit.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/include/asm/microcode.h | 1
- arch/x86/include/asm/microcode_amd.h | 2 +
- arch/x86/include/asm/msr-index.h | 1
- arch/x86/kernel/cpu/amd.c | 60 +++++++++++++++++++++++++++++++++++
- arch/x86/kernel/cpu/common.c | 2 +
- 5 files changed, 66 insertions(+)
-
---- a/arch/x86/include/asm/microcode.h
-+++ b/arch/x86/include/asm/microcode.h
-@@ -5,6 +5,7 @@
- #include <asm/cpu.h>
- #include <linux/earlycpio.h>
- #include <linux/initrd.h>
-+#include <asm/microcode_amd.h>
-
- struct ucode_patch {
- struct list_head plist;
---- a/arch/x86/include/asm/microcode_amd.h
-+++ b/arch/x86/include/asm/microcode_amd.h
-@@ -48,11 +48,13 @@ extern void __init load_ucode_amd_bsp(un
- extern void load_ucode_amd_ap(unsigned int family);
- extern int __init save_microcode_in_initrd_amd(unsigned int family);
- void reload_ucode_amd(unsigned int cpu);
-+extern void amd_check_microcode(void);
- #else
- static inline void __init load_ucode_amd_bsp(unsigned int family) {}
- static inline void load_ucode_amd_ap(unsigned int family) {}
- static inline int __init
- save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; }
- static inline void reload_ucode_amd(unsigned int cpu) {}
-+static inline void amd_check_microcode(void) {}
- #endif
- #endif /* _ASM_X86_MICROCODE_AMD_H */
---- a/arch/x86/include/asm/msr-index.h
-+++ b/arch/x86/include/asm/msr-index.h
-@@ -462,6 +462,7 @@
- #define MSR_AMD64_DE_CFG 0xc0011029
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
-+#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
-
- #define MSR_AMD64_BU_CFG2 0xc001102a
- #define MSR_AMD64_IBSFETCHCTL 0xc0011030
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -69,6 +69,11 @@ static const int amd_erratum_383[] =
- static const int amd_erratum_1054[] =
- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-
-+static const int amd_zenbleed[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
-+
- static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
- {
- int osvw_id = *erratum++;
-@@ -980,6 +985,47 @@ static void init_amd_zn(struct cpuinfo_x
- }
- }
-
-+static bool cpu_has_zenbleed_microcode(void)
-+{
-+ u32 good_rev = 0;
-+
-+ switch (boot_cpu_data.x86_model) {
-+ case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
-+ case 0x60 ... 0x67: good_rev = 0x0860010b; break;
-+ case 0x68 ... 0x6f: good_rev = 0x08608105; break;
-+ case 0x70 ... 0x7f: good_rev = 0x08701032; break;
-+ case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;
-+
-+ default:
-+ return false;
-+ break;
-+ }
-+
-+ if (boot_cpu_data.microcode < good_rev)
-+ return false;
-+
-+ return true;
-+}
-+
-+static void zenbleed_check(struct cpuinfo_x86 *c)
-+{
-+ if (!cpu_has_amd_erratum(c, amd_zenbleed))
-+ return;
-+
-+ if (cpu_has(c, X86_FEATURE_HYPERVISOR))
-+ return;
-+
-+ if (!cpu_has(c, X86_FEATURE_AVX))
-+ return;
-+
-+ if (!cpu_has_zenbleed_microcode()) {
-+ pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
-+ msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ } else {
-+ msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ }
-+}
-+
- static void init_amd(struct cpuinfo_x86 *c)
- {
- early_init_amd(c);
-@@ -1067,6 +1113,8 @@ static void init_amd(struct cpuinfo_x86
- msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
-
- check_null_seg_clears_base(c);
-+
-+ zenbleed_check(c);
- }
-
- #ifdef CONFIG_X86_32
-@@ -1180,3 +1228,15 @@ void set_dr_addr_mask(unsigned long mask
- break;
- }
- }
-+
-+static void zenbleed_check_cpu(void *unused)
-+{
-+ struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
-+
-+ zenbleed_check(c);
-+}
-+
-+void amd_check_microcode(void)
-+{
-+ on_each_cpu(zenbleed_check_cpu, NULL, 1);
-+}
---- a/arch/x86/kernel/cpu/common.c
-+++ b/arch/x86/kernel/cpu/common.c
-@@ -2125,6 +2125,8 @@ void microcode_check(void)
-
- perf_check_microcode();
-
-+ amd_check_microcode();
-+
- /* Reload CPUID max function as it might've changed. */
- info.cpuid_level = cpuid_eax(0);
-
+++ /dev/null
-From 334baad709246598bfd30587a0e98b0d90f3f596 Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:31:32 +0200
-Subject: x86/cpu/amd: Move the errata checking functionality up
-
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-
-Upstream commit: 8b6f687743dacce83dbb0c7cfacf88bab00f808a
-
-Avoid new and remove old forward declarations.
-
-No functional changes.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/kernel/cpu/amd.c | 139 ++++++++++++++++++++++------------------------
- 1 file changed, 67 insertions(+), 72 deletions(-)
-
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -26,11 +26,6 @@
-
- #include "cpu.h"
-
--static const int amd_erratum_383[];
--static const int amd_erratum_400[];
--static const int amd_erratum_1054[];
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
--
- /*
- * nodes_per_socket: Stores the number of nodes per socket.
- * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
-@@ -38,6 +33,73 @@ static bool cpu_has_amd_erratum(struct c
- */
- static u32 nodes_per_socket = 1;
-
-+/*
-+ * AMD errata checking
-+ *
-+ * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-+ * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-+ * have an OSVW id assigned, which it takes as first argument. Both take a
-+ * variable number of family-specific model-stepping ranges created by
-+ * AMD_MODEL_RANGE().
-+ *
-+ * Example:
-+ *
-+ * const int amd_erratum_319[] =
-+ * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-+ * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-+ * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-+ */
-+
-+#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
-+#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
-+#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-+ ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
-+#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
-+#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
-+#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
-+
-+static const int amd_erratum_400[] =
-+ AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-+ AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
-+
-+static const int amd_erratum_383[] =
-+ AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
-+
-+/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
-+static const int amd_erratum_1054[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-+
-+static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
-+{
-+ int osvw_id = *erratum++;
-+ u32 range;
-+ u32 ms;
-+
-+ if (osvw_id >= 0 && osvw_id < 65536 &&
-+ cpu_has(cpu, X86_FEATURE_OSVW)) {
-+ u64 osvw_len;
-+
-+ rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-+ if (osvw_id < osvw_len) {
-+ u64 osvw_bits;
-+
-+ rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-+ osvw_bits);
-+ return osvw_bits & (1ULL << (osvw_id & 0x3f));
-+ }
-+ }
-+
-+ /* OSVW unavailable or ID unknown, match family-model-stepping range */
-+ ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-+ while ((range = *erratum++))
-+ if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-+ (ms >= AMD_MODEL_RANGE_START(range)) &&
-+ (ms <= AMD_MODEL_RANGE_END(range)))
-+ return true;
-+
-+ return false;
-+}
-+
- static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
- {
- u32 gprs[8] = { 0 };
-@@ -1100,73 +1162,6 @@ static const struct cpu_dev amd_cpu_dev
-
- cpu_dev_register(amd_cpu_dev);
-
--/*
-- * AMD errata checking
-- *
-- * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-- * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-- * have an OSVW id assigned, which it takes as first argument. Both take a
-- * variable number of family-specific model-stepping ranges created by
-- * AMD_MODEL_RANGE().
-- *
-- * Example:
-- *
-- * const int amd_erratum_319[] =
-- * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-- * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-- * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-- */
--
--#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
--#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
--#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-- ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
--#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
--#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
--#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
--
--static const int amd_erratum_400[] =
-- AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-- AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
--
--static const int amd_erratum_383[] =
-- AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
--
--/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
--static const int amd_erratum_1054[] =
-- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
--
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
--{
-- int osvw_id = *erratum++;
-- u32 range;
-- u32 ms;
--
-- if (osvw_id >= 0 && osvw_id < 65536 &&
-- cpu_has(cpu, X86_FEATURE_OSVW)) {
-- u64 osvw_len;
--
-- rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-- if (osvw_id < osvw_len) {
-- u64 osvw_bits;
--
-- rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-- osvw_bits);
-- return osvw_bits & (1ULL << (osvw_id & 0x3f));
-- }
-- }
--
-- /* OSVW unavailable or ID unknown, match family-model-stepping range */
-- ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-- while ((range = *erratum++))
-- if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-- (ms >= AMD_MODEL_RANGE_START(range)) &&
-- (ms <= AMD_MODEL_RANGE_END(range)))
-- return true;
--
-- return false;
--}
--
- void set_dr_addr_mask(unsigned long mask, int dr)
- {
- if (!boot_cpu_has(X86_FEATURE_BPEXT))
+++ /dev/null
-From a32b0f0db3f396f1c9be2fe621e77c09ec3d8e7d Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Tue, 2 May 2023 19:53:50 +0200
-Subject: x86/microcode/AMD: Load late on both threads too
-
-From: Borislav Petkov (AMD) <bp@alien8.de>
-
-commit a32b0f0db3f396f1c9be2fe621e77c09ec3d8e7d upstream.
-
-Do the same as early loading - load on both threads.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Cc: <stable@kernel.org>
-Link: https://lore.kernel.org/r/20230605141332.25948-1-bp@alien8.de
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/kernel/cpu/microcode/amd.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/x86/kernel/cpu/microcode/amd.c
-+++ b/arch/x86/kernel/cpu/microcode/amd.c
-@@ -700,7 +700,7 @@ static enum ucode_state apply_microcode_
- rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
-
- /* need to apply patch? */
-- if (rev >= mc_amd->hdr.patch_id) {
-+ if (rev > mc_amd->hdr.patch_id) {
- ret = UCODE_OK;
- goto out;
- }
+++ /dev/null
-From b2d362e150f1a48e95b4224e6ad860948f48c158 Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:41:28 +0200
-Subject: x86/cpu/amd: Add a Zenbleed fix
-
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-
-Upstream commit: 522b1d69219d8f083173819fde04f994aa051a98
-
-Add a fix for the Zen2 VZEROUPPER data corruption bug where under
-certain circumstances executing VZEROUPPER can cause register
-corruption or leak data.
-
-The optimal fix is through microcode but in the case the proper
-microcode revision has not been applied, enable a fallback fix using
-a chicken bit.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/include/asm/microcode.h | 1
- arch/x86/include/asm/microcode_amd.h | 2 +
- arch/x86/include/asm/msr-index.h | 1
- arch/x86/kernel/cpu/amd.c | 60 +++++++++++++++++++++++++++++++++++
- arch/x86/kernel/cpu/common.c | 2 +
- 5 files changed, 66 insertions(+)
-
---- a/arch/x86/include/asm/microcode.h
-+++ b/arch/x86/include/asm/microcode.h
-@@ -5,6 +5,7 @@
- #include <asm/cpu.h>
- #include <linux/earlycpio.h>
- #include <linux/initrd.h>
-+#include <asm/microcode_amd.h>
-
- struct ucode_patch {
- struct list_head plist;
---- a/arch/x86/include/asm/microcode_amd.h
-+++ b/arch/x86/include/asm/microcode_amd.h
-@@ -48,11 +48,13 @@ extern void __init load_ucode_amd_bsp(un
- extern void load_ucode_amd_ap(unsigned int family);
- extern int __init save_microcode_in_initrd_amd(unsigned int family);
- void reload_ucode_amd(unsigned int cpu);
-+extern void amd_check_microcode(void);
- #else
- static inline void __init load_ucode_amd_bsp(unsigned int family) {}
- static inline void load_ucode_amd_ap(unsigned int family) {}
- static inline int __init
- save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; }
- static inline void reload_ucode_amd(unsigned int cpu) {}
-+static inline void amd_check_microcode(void) {}
- #endif
- #endif /* _ASM_X86_MICROCODE_AMD_H */
---- a/arch/x86/include/asm/msr-index.h
-+++ b/arch/x86/include/asm/msr-index.h
-@@ -543,6 +543,7 @@
- #define MSR_AMD64_DE_CFG 0xc0011029
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
-+#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
-
- #define MSR_AMD64_BU_CFG2 0xc001102a
- #define MSR_AMD64_IBSFETCHCTL 0xc0011030
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -70,6 +70,11 @@ static const int amd_erratum_383[] =
- static const int amd_erratum_1054[] =
- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-
-+static const int amd_zenbleed[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
-+
- static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
- {
- int osvw_id = *erratum++;
-@@ -978,6 +983,47 @@ static void init_amd_zn(struct cpuinfo_x
- }
- }
-
-+static bool cpu_has_zenbleed_microcode(void)
-+{
-+ u32 good_rev = 0;
-+
-+ switch (boot_cpu_data.x86_model) {
-+ case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
-+ case 0x60 ... 0x67: good_rev = 0x0860010b; break;
-+ case 0x68 ... 0x6f: good_rev = 0x08608105; break;
-+ case 0x70 ... 0x7f: good_rev = 0x08701032; break;
-+ case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;
-+
-+ default:
-+ return false;
-+ break;
-+ }
-+
-+ if (boot_cpu_data.microcode < good_rev)
-+ return false;
-+
-+ return true;
-+}
-+
-+static void zenbleed_check(struct cpuinfo_x86 *c)
-+{
-+ if (!cpu_has_amd_erratum(c, amd_zenbleed))
-+ return;
-+
-+ if (cpu_has(c, X86_FEATURE_HYPERVISOR))
-+ return;
-+
-+ if (!cpu_has(c, X86_FEATURE_AVX))
-+ return;
-+
-+ if (!cpu_has_zenbleed_microcode()) {
-+ pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
-+ msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ } else {
-+ msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ }
-+}
-+
- static void init_amd(struct cpuinfo_x86 *c)
- {
- early_init_amd(c);
-@@ -1067,6 +1113,8 @@ static void init_amd(struct cpuinfo_x86
- msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
-
- check_null_seg_clears_base(c);
-+
-+ zenbleed_check(c);
- }
-
- #ifdef CONFIG_X86_32
-@@ -1196,3 +1244,15 @@ u32 amd_get_highest_perf(void)
- return 255;
- }
- EXPORT_SYMBOL_GPL(amd_get_highest_perf);
-+
-+static void zenbleed_check_cpu(void *unused)
-+{
-+ struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
-+
-+ zenbleed_check(c);
-+}
-+
-+void amd_check_microcode(void)
-+{
-+ on_each_cpu(zenbleed_check_cpu, NULL, 1);
-+}
---- a/arch/x86/kernel/cpu/common.c
-+++ b/arch/x86/kernel/cpu/common.c
-@@ -2346,6 +2346,8 @@ void microcode_check(struct cpuinfo_x86
-
- perf_check_microcode();
-
-+ amd_check_microcode();
-+
- store_cpu_caps(&curr_info);
-
- if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
+++ /dev/null
-From 334baad709246598bfd30587a0e98b0d90f3f596 Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:31:32 +0200
-Subject: x86/cpu/amd: Move the errata checking functionality up
-
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-
-Upstream commit: 8b6f687743dacce83dbb0c7cfacf88bab00f808a
-
-Avoid new and remove old forward declarations.
-
-No functional changes.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/kernel/cpu/amd.c | 139 ++++++++++++++++++++++------------------------
- 1 file changed, 67 insertions(+), 72 deletions(-)
-
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -27,11 +27,6 @@
-
- #include "cpu.h"
-
--static const int amd_erratum_383[];
--static const int amd_erratum_400[];
--static const int amd_erratum_1054[];
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
--
- /*
- * nodes_per_socket: Stores the number of nodes per socket.
- * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
-@@ -39,6 +34,73 @@ static bool cpu_has_amd_erratum(struct c
- */
- static u32 nodes_per_socket = 1;
-
-+/*
-+ * AMD errata checking
-+ *
-+ * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-+ * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-+ * have an OSVW id assigned, which it takes as first argument. Both take a
-+ * variable number of family-specific model-stepping ranges created by
-+ * AMD_MODEL_RANGE().
-+ *
-+ * Example:
-+ *
-+ * const int amd_erratum_319[] =
-+ * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-+ * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-+ * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-+ */
-+
-+#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
-+#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
-+#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-+ ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
-+#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
-+#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
-+#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
-+
-+static const int amd_erratum_400[] =
-+ AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-+ AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
-+
-+static const int amd_erratum_383[] =
-+ AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
-+
-+/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
-+static const int amd_erratum_1054[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-+
-+static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
-+{
-+ int osvw_id = *erratum++;
-+ u32 range;
-+ u32 ms;
-+
-+ if (osvw_id >= 0 && osvw_id < 65536 &&
-+ cpu_has(cpu, X86_FEATURE_OSVW)) {
-+ u64 osvw_len;
-+
-+ rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-+ if (osvw_id < osvw_len) {
-+ u64 osvw_bits;
-+
-+ rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-+ osvw_bits);
-+ return osvw_bits & (1ULL << (osvw_id & 0x3f));
-+ }
-+ }
-+
-+ /* OSVW unavailable or ID unknown, match family-model-stepping range */
-+ ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-+ while ((range = *erratum++))
-+ if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-+ (ms >= AMD_MODEL_RANGE_START(range)) &&
-+ (ms <= AMD_MODEL_RANGE_END(range)))
-+ return true;
-+
-+ return false;
-+}
-+
- static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
- {
- u32 gprs[8] = { 0 };
-@@ -1100,73 +1162,6 @@ static const struct cpu_dev amd_cpu_dev
-
- cpu_dev_register(amd_cpu_dev);
-
--/*
-- * AMD errata checking
-- *
-- * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-- * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-- * have an OSVW id assigned, which it takes as first argument. Both take a
-- * variable number of family-specific model-stepping ranges created by
-- * AMD_MODEL_RANGE().
-- *
-- * Example:
-- *
-- * const int amd_erratum_319[] =
-- * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-- * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-- * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-- */
--
--#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
--#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
--#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-- ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
--#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
--#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
--#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
--
--static const int amd_erratum_400[] =
-- AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-- AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
--
--static const int amd_erratum_383[] =
-- AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
--
--/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
--static const int amd_erratum_1054[] =
-- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
--
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
--{
-- int osvw_id = *erratum++;
-- u32 range;
-- u32 ms;
--
-- if (osvw_id >= 0 && osvw_id < 65536 &&
-- cpu_has(cpu, X86_FEATURE_OSVW)) {
-- u64 osvw_len;
--
-- rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-- if (osvw_id < osvw_len) {
-- u64 osvw_bits;
--
-- rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-- osvw_bits);
-- return osvw_bits & (1ULL << (osvw_id & 0x3f));
-- }
-- }
--
-- /* OSVW unavailable or ID unknown, match family-model-stepping range */
-- ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-- while ((range = *erratum++))
-- if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-- (ms >= AMD_MODEL_RANGE_START(range)) &&
-- (ms <= AMD_MODEL_RANGE_END(range)))
-- return true;
--
-- return false;
--}
--
- void set_dr_addr_mask(unsigned long mask, int dr)
- {
- if (!boot_cpu_has(X86_FEATURE_BPEXT))
+++ /dev/null
-From 522b1d69219d8f083173819fde04f994aa051a98 Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:41:28 +0200
-Subject: x86/cpu/amd: Add a Zenbleed fix
-
-From: Borislav Petkov (AMD) <bp@alien8.de>
-
-commit 522b1d69219d8f083173819fde04f994aa051a98 upstream.
-
-Add a fix for the Zen2 VZEROUPPER data corruption bug where under
-certain circumstances executing VZEROUPPER can cause register
-corruption or leak data.
-
-The optimal fix is through microcode but in the case the proper
-microcode revision has not been applied, enable a fallback fix using
-a chicken bit.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/include/asm/microcode.h | 1
- arch/x86/include/asm/microcode_amd.h | 2 +
- arch/x86/include/asm/msr-index.h | 1
- arch/x86/kernel/cpu/amd.c | 60 +++++++++++++++++++++++++++++++++++
- arch/x86/kernel/cpu/common.c | 2 +
- 5 files changed, 66 insertions(+)
-
---- a/arch/x86/include/asm/microcode.h
-+++ b/arch/x86/include/asm/microcode.h
-@@ -5,6 +5,7 @@
- #include <asm/cpu.h>
- #include <linux/earlycpio.h>
- #include <linux/initrd.h>
-+#include <asm/microcode_amd.h>
-
- struct ucode_patch {
- struct list_head plist;
---- a/arch/x86/include/asm/microcode_amd.h
-+++ b/arch/x86/include/asm/microcode_amd.h
-@@ -48,11 +48,13 @@ extern void __init load_ucode_amd_bsp(un
- extern void load_ucode_amd_ap(unsigned int family);
- extern int __init save_microcode_in_initrd_amd(unsigned int family);
- void reload_ucode_amd(unsigned int cpu);
-+extern void amd_check_microcode(void);
- #else
- static inline void __init load_ucode_amd_bsp(unsigned int family) {}
- static inline void load_ucode_amd_ap(unsigned int family) {}
- static inline int __init
- save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; }
- static inline void reload_ucode_amd(unsigned int cpu) {}
-+static inline void amd_check_microcode(void) {}
- #endif
- #endif /* _ASM_X86_MICROCODE_AMD_H */
---- a/arch/x86/include/asm/msr-index.h
-+++ b/arch/x86/include/asm/msr-index.h
-@@ -545,6 +545,7 @@
- #define MSR_AMD64_DE_CFG 0xc0011029
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
- #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
-+#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
-
- #define MSR_AMD64_BU_CFG2 0xc001102a
- #define MSR_AMD64_IBSFETCHCTL 0xc0011030
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -70,6 +70,11 @@ static const int amd_erratum_383[] =
- static const int amd_erratum_1054[] =
- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-
-+static const int amd_zenbleed[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
-+ AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
-+
- static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
- {
- int osvw_id = *erratum++;
-@@ -978,6 +983,47 @@ static void init_amd_zn(struct cpuinfo_x
- }
- }
-
-+static bool cpu_has_zenbleed_microcode(void)
-+{
-+ u32 good_rev = 0;
-+
-+ switch (boot_cpu_data.x86_model) {
-+ case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
-+ case 0x60 ... 0x67: good_rev = 0x0860010b; break;
-+ case 0x68 ... 0x6f: good_rev = 0x08608105; break;
-+ case 0x70 ... 0x7f: good_rev = 0x08701032; break;
-+ case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;
-+
-+ default:
-+ return false;
-+ break;
-+ }
-+
-+ if (boot_cpu_data.microcode < good_rev)
-+ return false;
-+
-+ return true;
-+}
-+
-+static void zenbleed_check(struct cpuinfo_x86 *c)
-+{
-+ if (!cpu_has_amd_erratum(c, amd_zenbleed))
-+ return;
-+
-+ if (cpu_has(c, X86_FEATURE_HYPERVISOR))
-+ return;
-+
-+ if (!cpu_has(c, X86_FEATURE_AVX))
-+ return;
-+
-+ if (!cpu_has_zenbleed_microcode()) {
-+ pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
-+ msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ } else {
-+ msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
-+ }
-+}
-+
- static void init_amd(struct cpuinfo_x86 *c)
- {
- early_init_amd(c);
-@@ -1082,6 +1128,8 @@ static void init_amd(struct cpuinfo_x86
- if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
- cpu_has(c, X86_FEATURE_AUTOIBRS))
- WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
-+
-+ zenbleed_check(c);
- }
-
- #ifdef CONFIG_X86_32
-@@ -1230,3 +1278,15 @@ u32 amd_get_highest_perf(void)
- return 255;
- }
- EXPORT_SYMBOL_GPL(amd_get_highest_perf);
-+
-+static void zenbleed_check_cpu(void *unused)
-+{
-+ struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
-+
-+ zenbleed_check(c);
-+}
-+
-+void amd_check_microcode(void)
-+{
-+ on_each_cpu(zenbleed_check_cpu, NULL, 1);
-+}
---- a/arch/x86/kernel/cpu/common.c
-+++ b/arch/x86/kernel/cpu/common.c
-@@ -2341,6 +2341,8 @@ void microcode_check(struct cpuinfo_x86
-
- perf_check_microcode();
-
-+ amd_check_microcode();
-+
- store_cpu_caps(&curr_info);
-
- if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
+++ /dev/null
-From 8b6f687743dacce83dbb0c7cfacf88bab00f808a Mon Sep 17 00:00:00 2001
-From: "Borislav Petkov (AMD)" <bp@alien8.de>
-Date: Sat, 15 Jul 2023 13:31:32 +0200
-Subject: x86/cpu/amd: Move the errata checking functionality up
-
-From: Borislav Petkov (AMD) <bp@alien8.de>
-
-commit 8b6f687743dacce83dbb0c7cfacf88bab00f808a upstream.
-
-Avoid new and remove old forward declarations.
-
-No functional changes.
-
-Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/x86/kernel/cpu/amd.c | 139 ++++++++++++++++++++++------------------------
- 1 file changed, 67 insertions(+), 72 deletions(-)
-
---- a/arch/x86/kernel/cpu/amd.c
-+++ b/arch/x86/kernel/cpu/amd.c
-@@ -27,11 +27,6 @@
-
- #include "cpu.h"
-
--static const int amd_erratum_383[];
--static const int amd_erratum_400[];
--static const int amd_erratum_1054[];
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
--
- /*
- * nodes_per_socket: Stores the number of nodes per socket.
- * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
-@@ -39,6 +34,73 @@ static bool cpu_has_amd_erratum(struct c
- */
- static u32 nodes_per_socket = 1;
-
-+/*
-+ * AMD errata checking
-+ *
-+ * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-+ * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-+ * have an OSVW id assigned, which it takes as first argument. Both take a
-+ * variable number of family-specific model-stepping ranges created by
-+ * AMD_MODEL_RANGE().
-+ *
-+ * Example:
-+ *
-+ * const int amd_erratum_319[] =
-+ * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-+ * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-+ * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-+ */
-+
-+#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
-+#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
-+#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-+ ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
-+#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
-+#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
-+#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
-+
-+static const int amd_erratum_400[] =
-+ AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-+ AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
-+
-+static const int amd_erratum_383[] =
-+ AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
-+
-+/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
-+static const int amd_erratum_1054[] =
-+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
-+
-+static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
-+{
-+ int osvw_id = *erratum++;
-+ u32 range;
-+ u32 ms;
-+
-+ if (osvw_id >= 0 && osvw_id < 65536 &&
-+ cpu_has(cpu, X86_FEATURE_OSVW)) {
-+ u64 osvw_len;
-+
-+ rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-+ if (osvw_id < osvw_len) {
-+ u64 osvw_bits;
-+
-+ rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-+ osvw_bits);
-+ return osvw_bits & (1ULL << (osvw_id & 0x3f));
-+ }
-+ }
-+
-+ /* OSVW unavailable or ID unknown, match family-model-stepping range */
-+ ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-+ while ((range = *erratum++))
-+ if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-+ (ms >= AMD_MODEL_RANGE_START(range)) &&
-+ (ms <= AMD_MODEL_RANGE_END(range)))
-+ return true;
-+
-+ return false;
-+}
-+
- static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
- {
- u32 gprs[8] = { 0 };
-@@ -1115,73 +1177,6 @@ static const struct cpu_dev amd_cpu_dev
-
- cpu_dev_register(amd_cpu_dev);
-
--/*
-- * AMD errata checking
-- *
-- * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
-- * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
-- * have an OSVW id assigned, which it takes as first argument. Both take a
-- * variable number of family-specific model-stepping ranges created by
-- * AMD_MODEL_RANGE().
-- *
-- * Example:
-- *
-- * const int amd_erratum_319[] =
-- * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
-- * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
-- * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
-- */
--
--#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
--#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
--#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
-- ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
--#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
--#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
--#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
--
--static const int amd_erratum_400[] =
-- AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
-- AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
--
--static const int amd_erratum_383[] =
-- AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
--
--/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
--static const int amd_erratum_1054[] =
-- AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
--
--static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
--{
-- int osvw_id = *erratum++;
-- u32 range;
-- u32 ms;
--
-- if (osvw_id >= 0 && osvw_id < 65536 &&
-- cpu_has(cpu, X86_FEATURE_OSVW)) {
-- u64 osvw_len;
--
-- rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
-- if (osvw_id < osvw_len) {
-- u64 osvw_bits;
--
-- rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
-- osvw_bits);
-- return osvw_bits & (1ULL << (osvw_id & 0x3f));
-- }
-- }
--
-- /* OSVW unavailable or ID unknown, match family-model-stepping range */
-- ms = (cpu->x86_model << 4) | cpu->x86_stepping;
-- while ((range = *erratum++))
-- if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
-- (ms >= AMD_MODEL_RANGE_START(range)) &&
-- (ms <= AMD_MODEL_RANGE_END(range)))
-- return true;
--
-- return false;
--}
--
- static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask);
-
- static unsigned int amd_msr_dr_addr_masks[] = {
projects / thirdparty / kernel / stable-queue.git / commitdiff
