--- /dev/null
+From ad9bc1a6cdab7c55b58544351a4ff79ea25b134e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 8 Feb 2024 16:39:56 +0100
+Subject: arm64: dts: rockchip: add rs485 support on uart5 of
+ px30-ringneck-haikou
+
+From: Farouk Bouabid <farouk.bouabid@theobroma-systems.com>
+
+[ Upstream commit 5963d97aa780619ffb66cf4886c0ca1175ccbd3e ]
+
+A hardware switch can set the rs485 transceiver into half or full duplex
+mode.
+
+Switching to the half-duplex mode requires the user to enable em485 on
+uart5 using ioctl, DE/RE are both connected to GPIO0_B5 which is the
+RTS signal for uart0. Implement GPIO0_B5 as rts-gpios with RTS_ON_SEND
+option enabled (default) so that driver mode gets enabled while sending
+(RTS high) and receiver mode gets enabled while not sending (RTS low).
+
+In full-duplex mode (em485 is disabled), DE is connected to GPIO0_B5 and
+RE is grounded (enabled). Since GPIO0_B5 is implemented as rts-gpios, the
+driver mode gets enabled whenever we want to send something and RE is not
+affected (always enabled) in this case by the state of RTS.
+
+Signed-off-by: Farouk Bouabid <farouk.bouabid@theobroma-systems.com>
+Link: https://lore.kernel.org/r/20240208-dev-rx-enable-v6-2-39e68e17a339@theobroma-systems.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Stable-dep-of: 5ae4dca718ea ("arm64: dts: rockchip: Disable DMA for uart5 on px30-ringneck")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
+index de0a1f2af983b..56f73c17363fd 100644
+--- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
++++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
+@@ -226,6 +226,7 @@ &uart0 {
+
+ &uart5 {
+ pinctrl-0 = <&uart5_xfer>;
++ rts-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+--
+2.39.5
+
--- /dev/null
+From 6fe539a92b992cd0e6046ed47d14d939e12653dc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 18 Dec 2023 11:32:06 +0800
+Subject: drm/amdgpu: Check extended configuration space register when system
+ uses large bar
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ma Jun <Jun.Ma2@amd.com>
+
+[ Upstream commit e372baeb3d336b20fd9463784c577fd8824497cd ]
+
+Some customer platforms do not enable mmconfig for various reasons,
+such as bios bug, and therefore cannot access the GPU extend configuration
+space through mmio.
+
+When the system enters the d3cold state and resumes, the amdgpu driver
+fails to resume because the extend configuration space registers of
+GPU can't be restored. At this point, Usually we only see some failure
+dmesg log printed by amdgpu driver, it is difficult to find the root
+cause.
+
+Therefor print a warnning message if the system can't access the
+extended configuration space register when using large bar.
+
+Signed-off-by: Ma Jun <Jun.Ma2@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Stable-dep-of: 099bffc7cadf ("drm/amdgpu: disable BAR resize on Dell G5 SE")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 2e739b80cfccf..f1db7c9deaec2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1116,6 +1116,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
++ /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */
++ if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))
++ DRM_WARN("System can't access extended configuration space,please check!!\n");
++
+ /* skip if the bios has already enabled large BAR */
+ if (adev->gmc.real_vram_size &&
+ (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
+--
+2.39.5
+
--- /dev/null
+From 701bcda168c24550ed61ce1014538f96b39582d9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Feb 2025 10:55:05 -0500
+Subject: drm/amdgpu: disable BAR resize on Dell G5 SE
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+[ Upstream commit 099bffc7cadff40bfab1517c3461c53a7a38a0d7 ]
+
+There was a quirk added to add a workaround for a Sapphire
+RX 5600 XT Pulse that didn't allow BAR resizing. However,
+the quirk caused a regression with runtime pm on Dell laptops
+using those chips, rather than narrowing the scope of the
+resizing quirk, add a quirk to prevent amdgpu from resizing
+the BAR on those Dell platforms unless runtime pm is disabled.
+
+v2: update commit message, add runpm check
+
+Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/1707
+Fixes: 907830b0fc9e ("PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse")
+Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 5235053f443cef4210606e5fb71f99b915a9723d)
+Cc: stable@vger.kernel.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index f1db7c9deaec2..45dd6cbad81e7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1116,6 +1116,13 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
++ /* resizing on Dell G5 SE platforms causes problems with runtime pm */
++ if ((amdgpu_runtime_pm != 0) &&
++ adev->pdev->vendor == PCI_VENDOR_ID_ATI &&
++ adev->pdev->device == 0x731f &&
++ adev->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
++ return 0;
++
+ /* PCI_EXT_CAP_ID_VNDR extended capability is located at 0x100 */
+ if (!pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_VNDR))
+ DRM_WARN("System can't access extended configuration space,please check!!\n");
+--
+2.39.5
+
--- /dev/null
+From a63388ee5efe4f6f0a252710d904b1cdf4bbef81 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 14 Feb 2025 16:19:52 +0200
+Subject: drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL
+
+From: Imre Deak <imre.deak@intel.com>
+
+[ Upstream commit 166ce267ae3f96e439d8ccc838e8ec4d8b4dab73 ]
+
+Fix the port width programming in the DDI_BUF_CTL register on MTLP+,
+where this had an off-by-one error.
+
+Cc: <stable@vger.kernel.org> # v6.5+
+Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
+Reviewed-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Imre Deak <imre.deak@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-3-imre.deak@intel.com
+(cherry picked from commit b2ecdabe46d23db275f94cd7c46ca414a144818b)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
+ drivers/gpu/drm/i915/i915_reg.h | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
+index 9ac9df70e713c..893ecee3949ac 100644
+--- a/drivers/gpu/drm/i915/display/intel_ddi.c
++++ b/drivers/gpu/drm/i915/display/intel_ddi.c
+@@ -3242,7 +3242,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
+ intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
+ XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
+
+- buf_ctl |= DDI_PORT_WIDTH(lane_count);
++ buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
+
+ if (DISPLAY_VER(dev_priv) >= 20)
+ buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
+index 4e588fd1c82ed..589a10253d898 100644
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -5737,7 +5737,7 @@ enum skl_power_gate {
+ #define DDI_BUF_IS_IDLE (1 << 7)
+ #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
+ #define DDI_A_4_LANES (1 << 4)
+-#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
++#define DDI_PORT_WIDTH(width) (((width) == 3 ? 4 : ((width) - 1)) << 1)
+ #define DDI_PORT_WIDTH_MASK (7 << 1)
+ #define DDI_PORT_WIDTH_SHIFT 1
+ #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
+--
+2.39.5
+
--- /dev/null
+From 6a79f5d44c65bc626b9775014754988fbb5aed2d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Jan 2024 14:46:36 -0800
+Subject: drm/i915/xe2lpd: Move D2D enable/disable
+
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+
+[ Upstream commit d5c7854b50e634097da5dd6d221997ecf31ec8c1 ]
+
+Bits to enable/disable and check state for D2D moved from
+XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL (now named DDI_CTL_DE in the spec).
+Make the functions mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic
+to work with multiple reg location and bitfield layout.
+
+v2: Set/Clear XE2LPD_DDI_BUF_D2D_LINK_ENABLE in saved_port_bits when
+ enabling/disabling D2D so DDI_BUF_CTL is correctly programmed in
+ other places without overriding these bits (Clint)
+v3: Leave saved_port_bits alone as those bits are not meant to be
+ modified outside of the port initialization. Rather propagate the
+ additional bit in DDI_BUF_CTL to be set when that register is
+ written again after D2D is enabled.
+
+Cc: Matt Roper <matthew.d.roper@intel.com>
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240126224638.4132016-2-lucas.demarchi@intel.com
+Stable-dep-of: 166ce267ae3f ("drm/i915/ddi: Fix HDMI port width programming in DDI_BUF_CTL")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/i915/display/intel_ddi.c | 44 ++++++++++++++++++------
+ drivers/gpu/drm/i915/i915_reg.h | 2 ++
+ 2 files changed, 36 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
+index b347f90623494..9ac9df70e713c 100644
+--- a/drivers/gpu/drm/i915/display/intel_ddi.c
++++ b/drivers/gpu/drm/i915/display/intel_ddi.c
+@@ -2357,13 +2357,22 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
+ {
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
++ i915_reg_t reg;
++ u32 set_bits, wait_bits;
+
+- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
+- XELPDP_PORT_BUF_D2D_LINK_ENABLE);
++ if (DISPLAY_VER(dev_priv) >= 20) {
++ reg = DDI_BUF_CTL(port);
++ set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
++ wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
++ } else {
++ reg = XELPDP_PORT_BUF_CTL1(port);
++ set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
++ wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
++ }
+
+- if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
+- XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
+- drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
++ intel_de_rmw(dev_priv, reg, 0, set_bits);
++ if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
++ drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
+ port_name(port));
+ }
+ }
+@@ -2810,13 +2819,22 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
+ {
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ enum port port = encoder->port;
++ i915_reg_t reg;
++ u32 clr_bits, wait_bits;
+
+- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
+- XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
++ if (DISPLAY_VER(dev_priv) >= 20) {
++ reg = DDI_BUF_CTL(port);
++ clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
++ wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
++ } else {
++ reg = XELPDP_PORT_BUF_CTL1(port);
++ clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
++ wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
++ }
+
+- if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
+- XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
+- drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
++ intel_de_rmw(dev_priv, reg, clr_bits, 0);
++ if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
++ drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
+ port_name(port));
+ }
+
+@@ -3225,6 +3243,9 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
+ XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
+
+ buf_ctl |= DDI_PORT_WIDTH(lane_count);
++
++ if (DISPLAY_VER(dev_priv) >= 20)
++ buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
+ drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
+ buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+@@ -3449,6 +3470,9 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
+
+ /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
+ intel_dp->DP |= DDI_BUF_CTL_ENABLE;
++ if (DISPLAY_VER(dev_priv) >= 20)
++ intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
++
+ intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+ intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
+
+diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
+index aefad14ab27a4..4e588fd1c82ed 100644
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -5724,6 +5724,8 @@ enum skl_power_gate {
+ /* Known as DDI_CTL_DE in MTL+ */
+ #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
+ #define DDI_BUF_CTL_ENABLE (1 << 31)
++#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
++#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
+ #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
+ #define DDI_BUF_EMP_MASK (0xf << 24)
+ #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
+--
+2.39.5
+
--- /dev/null
+From 1b3aad19eac5e8f214c26d12c3fca516d8feae51 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 26 Feb 2025 15:18:39 -0500
+Subject: efi: Don't map the entire mokvar table to determine its size
+
+From: Peter Jones <pjones@redhat.com>
+
+[ Upstream commit 2b90e7ace79774a3540ce569e000388f8d22c9e0 ]
+
+Currently, when validating the mokvar table, we (re)map the entire table
+on each iteration of the loop, adding space as we discover new entries.
+If the table grows over a certain size, this fails due to limitations of
+early_memmap(), and we get a failure and traceback:
+
+ ------------[ cut here ]------------
+ WARNING: CPU: 0 PID: 0 at mm/early_ioremap.c:139 __early_ioremap+0xef/0x220
+ ...
+ Call Trace:
+ <TASK>
+ ? __early_ioremap+0xef/0x220
+ ? __warn.cold+0x93/0xfa
+ ? __early_ioremap+0xef/0x220
+ ? report_bug+0xff/0x140
+ ? early_fixup_exception+0x5d/0xb0
+ ? early_idt_handler_common+0x2f/0x3a
+ ? __early_ioremap+0xef/0x220
+ ? efi_mokvar_table_init+0xce/0x1d0
+ ? setup_arch+0x864/0xc10
+ ? start_kernel+0x6b/0xa10
+ ? x86_64_start_reservations+0x24/0x30
+ ? x86_64_start_kernel+0xed/0xf0
+ ? common_startup_64+0x13e/0x141
+ </TASK>
+ ---[ end trace 0000000000000000 ]---
+ mokvar: Failed to map EFI MOKvar config table pa=0x7c4c3000, size=265187.
+
+Mapping the entire structure isn't actually necessary, as we don't ever
+need more than one entry header mapped at once.
+
+Changes efi_mokvar_table_init() to only map each entry header, not the
+entire table, when determining the table size. Since we're not mapping
+any data past the variable name, it also changes the code to enforce
+that each variable name is NUL terminated, rather than attempting to
+verify it in place.
+
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Peter Jones <pjones@redhat.com>
+Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/firmware/efi/mokvar-table.c | 41 +++++++++--------------------
+ 1 file changed, 13 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/firmware/efi/mokvar-table.c b/drivers/firmware/efi/mokvar-table.c
+index 5ed0602c2f75f..d865cb1dbaad1 100644
+--- a/drivers/firmware/efi/mokvar-table.c
++++ b/drivers/firmware/efi/mokvar-table.c
+@@ -103,7 +103,6 @@ void __init efi_mokvar_table_init(void)
+ void *va = NULL;
+ unsigned long cur_offset = 0;
+ unsigned long offset_limit;
+- unsigned long map_size = 0;
+ unsigned long map_size_needed = 0;
+ unsigned long size;
+ struct efi_mokvar_table_entry *mokvar_entry;
+@@ -134,48 +133,34 @@ void __init efi_mokvar_table_init(void)
+ */
+ err = -EINVAL;
+ while (cur_offset + sizeof(*mokvar_entry) <= offset_limit) {
+- mokvar_entry = va + cur_offset;
+- map_size_needed = cur_offset + sizeof(*mokvar_entry);
+- if (map_size_needed > map_size) {
+- if (va)
+- early_memunmap(va, map_size);
+- /*
+- * Map a little more than the fixed size entry
+- * header, anticipating some data. It's safe to
+- * do so as long as we stay within current memory
+- * descriptor.
+- */
+- map_size = min(map_size_needed + 2*EFI_PAGE_SIZE,
+- offset_limit);
+- va = early_memremap(efi.mokvar_table, map_size);
+- if (!va) {
+- pr_err("Failed to map EFI MOKvar config table pa=0x%lx, size=%lu.\n",
+- efi.mokvar_table, map_size);
+- return;
+- }
+- mokvar_entry = va + cur_offset;
++ if (va)
++ early_memunmap(va, sizeof(*mokvar_entry));
++ va = early_memremap(efi.mokvar_table + cur_offset, sizeof(*mokvar_entry));
++ if (!va) {
++ pr_err("Failed to map EFI MOKvar config table pa=0x%lx, size=%zu.\n",
++ efi.mokvar_table + cur_offset, sizeof(*mokvar_entry));
++ return;
+ }
++ mokvar_entry = va;
+
+ /* Check for last sentinel entry */
+ if (mokvar_entry->name[0] == '\0') {
+ if (mokvar_entry->data_size != 0)
+ break;
+ err = 0;
++ map_size_needed = cur_offset + sizeof(*mokvar_entry);
+ break;
+ }
+
+- /* Sanity check that the name is null terminated */
+- size = strnlen(mokvar_entry->name,
+- sizeof(mokvar_entry->name));
+- if (size >= sizeof(mokvar_entry->name))
+- break;
++ /* Enforce that the name is NUL terminated */
++ mokvar_entry->name[sizeof(mokvar_entry->name) - 1] = '\0';
+
+ /* Advance to the next entry */
+- cur_offset = map_size_needed + mokvar_entry->data_size;
++ cur_offset += sizeof(*mokvar_entry) + mokvar_entry->data_size;
+ }
+
+ if (va)
+- early_memunmap(va, map_size);
++ early_memunmap(va, sizeof(*mokvar_entry));
+ if (err) {
+ pr_err("EFI MOKvar config table is not valid\n");
+ return;
+--
+2.39.5
+
--- /dev/null
+From f245ccf645865298f8b23f249953b7cddcdd3180 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 1 Oct 2024 11:32:00 -0500
+Subject: ibmvnic: Inspect header requirements before using scrq direct
+
+From: Nick Child <nnac123@linux.ibm.com>
+
+[ Upstream commit de390657b5d6f7deb9d1d36aaf45f02ba51ec9dc ]
+
+Previously, the TX header requirement for standard frames was ignored.
+This requirement is a bitstring sent from the VIOS which maps to the
+type of header information needed during TX. If no header information,
+is needed then send subcrq direct can be used (which can be more
+performant).
+
+This bitstring was previously ignored for standard packets (AKA non LSO,
+non CSO) due to the belief that the bitstring was over-cautionary. It
+turns out that there are some configurations where the backing device
+does need header information for transmission of standard packets. If
+the information is not supplied then this causes continuous "Adapter
+error" transport events. Therefore, this bitstring should be respected
+and observed before considering the use of send subcrq direct.
+
+Fixes: 74839f7a8268 ("ibmvnic: Introduce send sub-crq direct")
+Signed-off-by: Nick Child <nnac123@linux.ibm.com>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://patch.msgid.link/20241001163200.1802522-2-nnac123@linux.ibm.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/ibm/ibmvnic.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
+index 4bcfdf6e6d3f2..05f410999a5a1 100644
+--- a/drivers/net/ethernet/ibm/ibmvnic.c
++++ b/drivers/net/ethernet/ibm/ibmvnic.c
+@@ -2490,9 +2490,11 @@ static netdev_tx_t ibmvnic_xmit(struct sk_buff *skb, struct net_device *netdev)
+ /* if we are going to send_subcrq_direct this then we need to
+ * update the checksum before copying the data into ltb. Essentially
+ * these packets force disable CSO so that we can guarantee that
+- * FW does not need header info and we can send direct.
++ * FW does not need header info and we can send direct. Also, vnic
++ * server must be able to xmit standard packets without header data
+ */
+- if (!skb_is_gso(skb) && !ind_bufp->index && !netdev_xmit_more()) {
++ if (*hdrs == 0 && !skb_is_gso(skb) &&
++ !ind_bufp->index && !netdev_xmit_more()) {
+ use_scrq_send_direct = true;
+ if (skb->ip_summed == CHECKSUM_PARTIAL &&
+ skb_checksum_help(skb))
+--
+2.39.5
+
--- /dev/null
+From 29b990675b5f6729a98c69edc4e45d15bf2f2bfc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Aug 2024 16:18:09 -0500
+Subject: ibmvnic: Perform tx CSO during send scrq direct
+
+From: Nick Child <nnac123@linux.ibm.com>
+
+[ Upstream commit e633e32b60fd6701bed73599b273a2a03621ea54 ]
+
+During initialization with the vnic server, a bitstring is communicated
+to the client regarding header info needed during CSO (See "VNIC
+Capabilities" in PAPR). Most of the time, to be safe, vnic server
+requests header info for CSO. When header info is needed, multiple TX
+descriptors are required per skb; This limits the driver to use
+send_subcrq_indirect instead of send_subcrq_direct.
+
+Previously, the vnic server request for header info was ignored. This
+allowed the use of send_sub_crq_direct. Transmissions were successful
+because the bitstring returned by vnic server is broad and over
+cautionary. It was observed that mlx backing devices could actually
+transmit and handle CSO packets without the vnic server receiving
+header info (despite the fact that the bitstring requested it).
+
+There was a trust issue: The bitstring was overcautionary. This extra
+precaution (requesting header info when the backing device may not use
+it) comes at the cost of performance (using direct vs indirect hcalls
+has a 30% delta in small packet RR transaction rate). So it has been
+requested that the vnic server team tries to ensure that the bitstring
+is more exact. In the meantime, disable CSO when it is possible to use
+the skb in the send_subcrq_direct path. In other words, calculate the
+checksum before handing the packet to FW when the packet is not
+segmented and xmit_more is false.
+
+Since the code path is only possible if the skb is non GSO and xmit_more
+is false, the cost of doing checksum in the send_subcrq_direct path is
+minimal. Any large segmented skb will have xmit_more set to true more
+frequently and it is inexpensive to do checksumming on a small skb.
+The worst-case workload would be a 9000 MTU TCP_RR test with close
+to MTU sized packets (and TSO off). This allows xmit_more to be false
+more frequently and open the code path up to use send_subcrq_direct.
+Observing trace data (graph-time = 1) and packet rate with this workload
+shows minimal performance degradation:
+
+1. NIC does checksum w headers, safely use send_subcrq_indirect:
+ - Packet rate: 631k txs
+ - Trace data:
+ ibmvnic_xmit = 44344685.87 us / 6234576 hits = AVG 7.11 us
+ skb_checksum_help = 4.07 us / 2 hits = AVG 2.04 us
+ ^ Notice hits, tracing this just for reassurance
+ ibmvnic_tx_scrq_flush = 33040649.69 us / 5638441 hits = AVG 5.86 us
+ send_subcrq_indirect = 37438922.24 us / 6030859 hits = AVG 6.21 us
+
+2. NIC does checksum w/o headers, dangerously use send_subcrq_direct:
+ - Packet rate: 831k txs
+ - Trace data:
+ ibmvnic_xmit = 48940092.29 us / 8187630 hits = AVG 5.98 us
+ skb_checksum_help = 2.03 us / 1 hits = AVG 2.03
+ ibmvnic_tx_scrq_flush = 31141879.57 us / 7948960 hits = AVG 3.92 us
+ send_subcrq_indirect = 8412506.03 us / 728781 hits = AVG 11.54
+ ^ notice hits is much lower b/c send_subcrq_direct was called
+ ^ wasn't traceable
+
+3. driver does checksum, safely use send_subcrq_direct (THIS PATCH):
+ - Packet rate: 829k txs
+ - Trace data:
+ ibmvnic_xmit = 56696077.63 us / 8066168 hits = AVG 7.03 us
+ skb_checksum_help = 8587456.16 us / 7526072 hits = AVG 1.14 us
+ ibmvnic_tx_scrq_flush = 30219545.55 us / 7782409 hits = AVG 3.88 us
+ send_subcrq_indirect = 8638326.44 us / 763693 hits = AVG 11.31 us
+
+When the bitstring ever specifies that CSO does not require headers
+(dependent on VIOS vnic server changes), then this patch should be
+removed and replaced with one that investigates the bitstring before
+using send_subcrq_direct.
+
+Signed-off-by: Nick Child <nnac123@linux.ibm.com>
+Link: https://patch.msgid.link/20240807211809.1259563-8-nnac123@linux.ibm.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Stable-dep-of: de390657b5d6 ("ibmvnic: Inspect header requirements before using scrq direct")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/ibm/ibmvnic.c | 19 +++++++++++++++++--
+ 1 file changed, 17 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
+index 4f18addc191b8..4bcfdf6e6d3f2 100644
+--- a/drivers/net/ethernet/ibm/ibmvnic.c
++++ b/drivers/net/ethernet/ibm/ibmvnic.c
+@@ -2427,6 +2427,7 @@ static netdev_tx_t ibmvnic_xmit(struct sk_buff *skb, struct net_device *netdev)
+ unsigned int skblen;
+ union sub_crq tx_crq;
+ unsigned int offset;
++ bool use_scrq_send_direct = false;
+ int num_entries = 1;
+ unsigned char *dst;
+ int bufidx = 0;
+@@ -2486,6 +2487,18 @@ static netdev_tx_t ibmvnic_xmit(struct sk_buff *skb, struct net_device *netdev)
+ memset(dst, 0, tx_pool->buf_size);
+ data_dma_addr = ltb->addr + offset;
+
++ /* if we are going to send_subcrq_direct this then we need to
++ * update the checksum before copying the data into ltb. Essentially
++ * these packets force disable CSO so that we can guarantee that
++ * FW does not need header info and we can send direct.
++ */
++ if (!skb_is_gso(skb) && !ind_bufp->index && !netdev_xmit_more()) {
++ use_scrq_send_direct = true;
++ if (skb->ip_summed == CHECKSUM_PARTIAL &&
++ skb_checksum_help(skb))
++ use_scrq_send_direct = false;
++ }
++
+ if (skb_shinfo(skb)->nr_frags) {
+ int cur, i;
+
+@@ -2571,11 +2584,13 @@ static netdev_tx_t ibmvnic_xmit(struct sk_buff *skb, struct net_device *netdev)
+ tx_crq.v1.flags1 |= IBMVNIC_TX_LSO;
+ tx_crq.v1.mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
+ hdrs += 2;
+- } else if (!ind_bufp->index && !netdev_xmit_more()) {
+- ind_bufp->indir_arr[0] = tx_crq;
++ } else if (use_scrq_send_direct) {
++ /* See above comment, CSO disabled with direct xmit */
++ tx_crq.v1.flags1 &= ~(IBMVNIC_TX_CHKSUM_OFFLOAD);
+ ind_bufp->index = 1;
+ tx_buff->num_entries = 1;
+ netdev_tx_sent_queue(txq, skb->len);
++ ind_bufp->indir_arr[0] = tx_crq;
+ lpar_rc = ibmvnic_tx_scrq_flush(adapter, tx_scrq, false);
+ if (lpar_rc != H_SUCCESS)
+ goto tx_err;
+--
+2.39.5
+
--- /dev/null
+From c83672651f924e42f66917093d844b84b1017328 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 1 Sep 2024 14:28:00 +0300
+Subject: net: enetc: Remove setting of RX software timestamp
+
+From: Gal Pressman <gal@nvidia.com>
+
+[ Upstream commit 3dd261ca7f84c65af40f37825bf1cbb0cf3d5583 ]
+
+The responsibility for reporting of RX software timestamp has moved to
+the core layer (see __ethtool_get_ts_info()), remove usage from the
+device drivers.
+
+Reviewed-by: Carolina Jubran <cjubran@nvidia.com>
+Reviewed-by: Rahul Rameshbabu <rrameshbabu@nvidia.com>
+Signed-off-by: Gal Pressman <gal@nvidia.com>
+Reviewed-by: Wei Fang <wei.fang@nxp.com>
+Link: https://patch.msgid.link/20240901112803.212753-13-gal@nvidia.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Stable-dep-of: a562d0c4a893 ("net: enetc: VFs do not support HWTSTAMP_TX_ONESTEP_SYNC")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/freescale/enetc/enetc_ethtool.c | 10 ++--------
+ 1 file changed, 2 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
+index e993ed04ab572..aa7d427e654ff 100644
+--- a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
+@@ -846,17 +846,13 @@ static int enetc_get_ts_info(struct net_device *ndev,
+ if (phc_idx) {
+ info->phc_index = *phc_idx;
+ symbol_put(enetc_phc_index);
+- } else {
+- info->phc_index = -1;
+ }
+
+ #ifdef CONFIG_FSL_ENETC_PTP_CLOCK
+ info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
+ SOF_TIMESTAMPING_RX_HARDWARE |
+ SOF_TIMESTAMPING_RAW_HARDWARE |
+- SOF_TIMESTAMPING_TX_SOFTWARE |
+- SOF_TIMESTAMPING_RX_SOFTWARE |
+- SOF_TIMESTAMPING_SOFTWARE;
++ SOF_TIMESTAMPING_TX_SOFTWARE;
+
+ info->tx_types = (1 << HWTSTAMP_TX_OFF) |
+ (1 << HWTSTAMP_TX_ON) |
+@@ -864,9 +860,7 @@ static int enetc_get_ts_info(struct net_device *ndev,
+ info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
+ (1 << HWTSTAMP_FILTER_ALL);
+ #else
+- info->so_timestamping = SOF_TIMESTAMPING_RX_SOFTWARE |
+- SOF_TIMESTAMPING_TX_SOFTWARE |
+- SOF_TIMESTAMPING_SOFTWARE;
++ info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE;
+ #endif
+ return 0;
+ }
+--
+2.39.5
+
--- /dev/null
+From 48fd4939dbae6378daf9de5de8ceb6823eca8024 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 12 Sep 2024 18:37:40 +0100
+Subject: net: enetc: Replace ifdef with IS_ENABLED
+
+From: Martyn Welch <martyn.welch@collabora.com>
+
+[ Upstream commit 9c699a8f3b273c62f7b364ff999e873501a1e834 ]
+
+The enetc driver uses ifdefs when checking whether
+CONFIG_FSL_ENETC_PTP_CLOCK is enabled in a number of places. This works
+if the driver is built-in but fails if the driver is available as a
+kernel module. Replace the instances of ifdef with use of the IS_ENABLED
+macro, that will evaluate as true when this feature is built as a kernel
+module and follows the kernel's coding style.
+
+Reviewed-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
+Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://patch.msgid.link/20240912173742.484549-1-martyn.welch@collabora.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Stable-dep-of: a562d0c4a893 ("net: enetc: VFs do not support HWTSTAMP_TX_ONESTEP_SYNC")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/freescale/enetc/enetc.c | 22 ++++++++-----------
+ drivers/net/ethernet/freescale/enetc/enetc.h | 9 +++-----
+ .../ethernet/freescale/enetc/enetc_ethtool.c | 12 ++++++----
+ 3 files changed, 20 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c b/drivers/net/ethernet/freescale/enetc/enetc.c
+index 9aa57134f460c..30653830981d1 100644
+--- a/drivers/net/ethernet/freescale/enetc/enetc.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc.c
+@@ -1023,7 +1023,6 @@ static int enetc_refill_rx_ring(struct enetc_bdr *rx_ring, const int buff_cnt)
+ return j;
+ }
+
+-#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
+ static void enetc_get_rx_tstamp(struct net_device *ndev,
+ union enetc_rx_bd *rxbd,
+ struct sk_buff *skb)
+@@ -1047,7 +1046,6 @@ static void enetc_get_rx_tstamp(struct net_device *ndev,
+ shhwtstamps->hwtstamp = ns_to_ktime(tstamp);
+ }
+ }
+-#endif
+
+ static void enetc_get_offloads(struct enetc_bdr *rx_ring,
+ union enetc_rx_bd *rxbd, struct sk_buff *skb)
+@@ -1087,10 +1085,9 @@ static void enetc_get_offloads(struct enetc_bdr *rx_ring,
+ __vlan_hwaccel_put_tag(skb, tpid, le16_to_cpu(rxbd->r.vlan_opt));
+ }
+
+-#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
+- if (priv->active_offloads & ENETC_F_RX_TSTAMP)
++ if (IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK) &&
++ (priv->active_offloads & ENETC_F_RX_TSTAMP))
+ enetc_get_rx_tstamp(rx_ring->ndev, rxbd, skb);
+-#endif
+ }
+
+ /* This gets called during the non-XDP NAPI poll cycle as well as on XDP_PASS,
+@@ -2956,7 +2953,6 @@ void enetc_set_features(struct net_device *ndev, netdev_features_t features)
+ }
+ EXPORT_SYMBOL_GPL(enetc_set_features);
+
+-#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
+ static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr)
+ {
+ struct enetc_ndev_priv *priv = netdev_priv(ndev);
+@@ -3025,17 +3021,17 @@ static int enetc_hwtstamp_get(struct net_device *ndev, struct ifreq *ifr)
+ return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
+ -EFAULT : 0;
+ }
+-#endif
+
+ int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
+ {
+ struct enetc_ndev_priv *priv = netdev_priv(ndev);
+-#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
+- if (cmd == SIOCSHWTSTAMP)
+- return enetc_hwtstamp_set(ndev, rq);
+- if (cmd == SIOCGHWTSTAMP)
+- return enetc_hwtstamp_get(ndev, rq);
+-#endif
++
++ if (IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK)) {
++ if (cmd == SIOCSHWTSTAMP)
++ return enetc_hwtstamp_set(ndev, rq);
++ if (cmd == SIOCGHWTSTAMP)
++ return enetc_hwtstamp_get(ndev, rq);
++ }
+
+ if (!priv->phylink)
+ return -EOPNOTSUPP;
+diff --git a/drivers/net/ethernet/freescale/enetc/enetc.h b/drivers/net/ethernet/freescale/enetc/enetc.h
+index fcadb0848d254..860ecee302f1a 100644
+--- a/drivers/net/ethernet/freescale/enetc/enetc.h
++++ b/drivers/net/ethernet/freescale/enetc/enetc.h
+@@ -184,10 +184,9 @@ static inline union enetc_rx_bd *enetc_rxbd(struct enetc_bdr *rx_ring, int i)
+ {
+ int hw_idx = i;
+
+-#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
+- if (rx_ring->ext_en)
++ if (IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK) && rx_ring->ext_en)
+ hw_idx = 2 * i;
+-#endif
++
+ return &(((union enetc_rx_bd *)rx_ring->bd_base)[hw_idx]);
+ }
+
+@@ -199,10 +198,8 @@ static inline void enetc_rxbd_next(struct enetc_bdr *rx_ring,
+
+ new_rxbd++;
+
+-#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
+- if (rx_ring->ext_en)
++ if (IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK) && rx_ring->ext_en)
+ new_rxbd++;
+-#endif
+
+ if (unlikely(++new_index == rx_ring->bd_count)) {
+ new_rxbd = rx_ring->bd_base;
+diff --git a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
+index aa7d427e654ff..39fbc465746f7 100644
+--- a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
+@@ -848,7 +848,12 @@ static int enetc_get_ts_info(struct net_device *ndev,
+ symbol_put(enetc_phc_index);
+ }
+
+-#ifdef CONFIG_FSL_ENETC_PTP_CLOCK
++ if (!IS_ENABLED(CONFIG_FSL_ENETC_PTP_CLOCK)) {
++ info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE;
++
++ return 0;
++ }
++
+ info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
+ SOF_TIMESTAMPING_RX_HARDWARE |
+ SOF_TIMESTAMPING_RAW_HARDWARE |
+@@ -857,11 +862,10 @@ static int enetc_get_ts_info(struct net_device *ndev,
+ info->tx_types = (1 << HWTSTAMP_TX_OFF) |
+ (1 << HWTSTAMP_TX_ON) |
+ (1 << HWTSTAMP_TX_ONESTEP_SYNC);
++
+ info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
+ (1 << HWTSTAMP_FILTER_ALL);
+-#else
+- info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE;
+-#endif
++
+ return 0;
+ }
+
+--
+2.39.5
+
--- /dev/null
+From c800e17acff881d5a9294e9b367477737cffb586 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 24 Feb 2025 19:12:47 +0800
+Subject: net: enetc: VFs do not support HWTSTAMP_TX_ONESTEP_SYNC
+
+From: Wei Fang <wei.fang@nxp.com>
+
+[ Upstream commit a562d0c4a893eae3ea51d512c4d90ab858a6b7ec ]
+
+Actually ENETC VFs do not support HWTSTAMP_TX_ONESTEP_SYNC because only
+ENETC PF can access PMa_SINGLE_STEP registers. And there will be a crash
+if VFs are used to test one-step timestamp, the crash log as follows.
+
+[ 129.110909] Unable to handle kernel paging request at virtual address 00000000000080c0
+[ 129.287769] Call trace:
+[ 129.290219] enetc_port_mac_wr+0x30/0xec (P)
+[ 129.294504] enetc_start_xmit+0xda4/0xe74
+[ 129.298525] enetc_xmit+0x70/0xec
+[ 129.301848] dev_hard_start_xmit+0x98/0x118
+
+Fixes: 41514737ecaa ("enetc: add get_ts_info interface for ethtool")
+Cc: stable@vger.kernel.org
+Signed-off-by: Wei Fang <wei.fang@nxp.com>
+Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Link: https://patch.msgid.link/20250224111251.1061098-5-wei.fang@nxp.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/freescale/enetc/enetc.c | 3 +++
+ drivers/net/ethernet/freescale/enetc/enetc_ethtool.c | 7 +++++--
+ 2 files changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c b/drivers/net/ethernet/freescale/enetc/enetc.c
+index 30653830981d1..8feb7d4226bb5 100644
+--- a/drivers/net/ethernet/freescale/enetc/enetc.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc.c
+@@ -2971,6 +2971,9 @@ static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr)
+ new_offloads |= ENETC_F_TX_TSTAMP;
+ break;
+ case HWTSTAMP_TX_ONESTEP_SYNC:
++ if (!enetc_si_is_pf(priv->si))
++ return -EOPNOTSUPP;
++
+ new_offloads &= ~ENETC_F_TX_TSTAMP_MASK;
+ new_offloads |= ENETC_F_TX_ONESTEP_SYNC_TSTAMP;
+ break;
+diff --git a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
+index 39fbc465746f7..1e3e0073276ec 100644
+--- a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
+@@ -840,6 +840,7 @@ static int enetc_set_coalesce(struct net_device *ndev,
+ static int enetc_get_ts_info(struct net_device *ndev,
+ struct ethtool_ts_info *info)
+ {
++ struct enetc_ndev_priv *priv = netdev_priv(ndev);
+ int *phc_idx;
+
+ phc_idx = symbol_get(enetc_phc_index);
+@@ -860,8 +861,10 @@ static int enetc_get_ts_info(struct net_device *ndev,
+ SOF_TIMESTAMPING_TX_SOFTWARE;
+
+ info->tx_types = (1 << HWTSTAMP_TX_OFF) |
+- (1 << HWTSTAMP_TX_ON) |
+- (1 << HWTSTAMP_TX_ONESTEP_SYNC);
++ (1 << HWTSTAMP_TX_ON);
++
++ if (enetc_si_is_pf(priv->si))
++ info->tx_types |= (1 << HWTSTAMP_TX_ONESTEP_SYNC);
+
+ info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
+ (1 << HWTSTAMP_FILTER_ALL);
+--
+2.39.5
+
--- /dev/null
+From c2afb4898c8448858752f306235f69fadca6bb30 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 1 Feb 2025 14:59:02 -0500
+Subject: NFS: O_DIRECT writes must check and adjust the file length
+
+From: Trond Myklebust <trond.myklebust@hammerspace.com>
+
+[ Upstream commit fcf857ee1958e9247298251f7615d0c76f1e9b38 ]
+
+While it is uncommon for delegations to be held while O_DIRECT writes
+are in progress, it is possible. The xfstests generic/647 and
+generic/729 both end up triggering that state, and end up failing due to
+the fact that the file size is not adjusted.
+
+Reported-by: Chuck Lever <chuck.lever@oracle.com>
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=219738
+Cc: stable@vger.kernel.org
+Signed-off-by: Trond Myklebust <trond.myklebust@hammerspace.com>
+Signed-off-by: Anna Schumaker <anna.schumaker@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/nfs/direct.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/fs/nfs/direct.c b/fs/nfs/direct.c
+index 258521d5125ed..a1ff4a4f5380e 100644
+--- a/fs/nfs/direct.c
++++ b/fs/nfs/direct.c
+@@ -130,6 +130,20 @@ static void nfs_direct_truncate_request(struct nfs_direct_req *dreq,
+ dreq->count = req_start;
+ }
+
++static void nfs_direct_file_adjust_size_locked(struct inode *inode,
++ loff_t offset, size_t count)
++{
++ loff_t newsize = offset + (loff_t)count;
++ loff_t oldsize = i_size_read(inode);
++
++ if (newsize > oldsize) {
++ i_size_write(inode, newsize);
++ NFS_I(inode)->cache_validity &= ~NFS_INO_INVALID_SIZE;
++ trace_nfs_size_grow(inode, newsize);
++ nfs_inc_stats(inode, NFSIOS_EXTENDWRITE);
++ }
++}
++
+ /**
+ * nfs_swap_rw - NFS address space operation for swap I/O
+ * @iocb: target I/O control block
+@@ -728,6 +742,7 @@ static void nfs_direct_write_completion(struct nfs_pgio_header *hdr)
+ struct nfs_direct_req *dreq = hdr->dreq;
+ struct nfs_commit_info cinfo;
+ struct nfs_page *req = nfs_list_entry(hdr->pages.next);
++ struct inode *inode = dreq->inode;
+ int flags = NFS_ODIRECT_DONE;
+
+ trace_nfs_direct_write_completion(dreq);
+@@ -749,6 +764,10 @@ static void nfs_direct_write_completion(struct nfs_pgio_header *hdr)
+ }
+ spin_unlock(&dreq->lock);
+
++ spin_lock(&inode->i_lock);
++ nfs_direct_file_adjust_size_locked(inode, dreq->io_start, dreq->count);
++ spin_unlock(&inode->i_lock);
++
+ while (!list_empty(&hdr->pages)) {
+
+ req = nfs_list_entry(hdr->pages.next);
+--
+2.39.5
+
--- /dev/null
+From d6bb44688fa0585c8488b6a3f24583ad66ed8c2f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 18 Sep 2023 15:15:21 +0200
+Subject: RISC-V: Enable cbo.zero in usermode
+
+From: Andrew Jones <ajones@ventanamicro.com>
+
+[ Upstream commit 43c16d51a19b0ba2ed66978d5924d486ec1e42bc ]
+
+When Zicboz is present, enable its instruction (cbo.zero) in
+usermode by setting its respective senvcfg bit. We don't bother
+trying to set this bit per-task, which would also require an
+interface for tasks to request enabling and/or disabling. Instead,
+permanently set the bit for each hart which has the extension when
+bringing it online.
+
+This patch also introduces riscv_cpu_has_extension_[un]likely()
+functions to check a specific hart's ISA bitmap for extensions.
+Prior to checking the specific hart's bitmap in these functions
+we try the bitmap which represents the LCD of extensions, but only
+when we know it will use its optimized, alternatives path by gating
+its call on CONFIG_RISCV_ALTERNATIVE. When alternatives are used, the
+compiler ensures that the invocation of the LCD search becomes a
+constant true or false. When it's true, even the new functions will
+completely vanish from their callsites. OTOH, when the LCD check is
+false, we need to do a search of the hart's ISA bitmap. Had we also
+checked the LCD bitmap without the use of alternatives, then we would
+have ended up with two bitmap searches instead of one.
+
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20230918131518.56803-10-ajones@ventanamicro.com
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Stable-dep-of: 564fc8eb6f78 ("riscv: signal: fix signal_minsigstksz")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/include/asm/cpufeature.h | 1 +
+ arch/riscv/include/asm/csr.h | 1 +
+ arch/riscv/include/asm/hwcap.h | 16 ++++++++++++++++
+ arch/riscv/kernel/cpufeature.c | 6 ++++++
+ arch/riscv/kernel/setup.c | 4 ++++
+ arch/riscv/kernel/smpboot.c | 4 ++++
+ 6 files changed, 32 insertions(+)
+
+diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
+index d0345bd659c94..13b7d35648a9c 100644
+--- a/arch/riscv/include/asm/cpufeature.h
++++ b/arch/riscv/include/asm/cpufeature.h
+@@ -31,5 +31,6 @@ DECLARE_PER_CPU(long, misaligned_access_speed);
+ extern struct riscv_isainfo hart_isa[NR_CPUS];
+
+ void check_unaligned_access(int cpu);
++void riscv_user_isa_enable(void);
+
+ #endif
+diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
+index 777cb8299551c..5fba25db82d2a 100644
+--- a/arch/riscv/include/asm/csr.h
++++ b/arch/riscv/include/asm/csr.h
+@@ -275,6 +275,7 @@
+ #define CSR_SIE 0x104
+ #define CSR_STVEC 0x105
+ #define CSR_SCOUNTEREN 0x106
++#define CSR_SENVCFG 0x10a
+ #define CSR_SSCRATCH 0x140
+ #define CSR_SEPC 0x141
+ #define CSR_SCAUSE 0x142
+diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
+index f4157034efa9c..e215d3399a179 100644
+--- a/arch/riscv/include/asm/hwcap.h
++++ b/arch/riscv/include/asm/hwcap.h
+@@ -70,6 +70,7 @@
+ #ifndef __ASSEMBLY__
+
+ #include <linux/jump_label.h>
++#include <asm/cpufeature.h>
+
+ unsigned long riscv_get_elf_hwcap(void);
+
+@@ -137,6 +138,21 @@ riscv_has_extension_unlikely(const unsigned long ext)
+ return true;
+ }
+
++static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
++{
++ if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
++ return true;
++
++ return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
++}
++
++static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
++{
++ if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
++ return true;
++
++ return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
++}
+ #endif
+
+ #endif /* _ASM_RISCV_HWCAP_H */
+diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
+index bb5fb2b820a21..a6b6bbf3f8598 100644
+--- a/arch/riscv/kernel/cpufeature.c
++++ b/arch/riscv/kernel/cpufeature.c
+@@ -676,6 +676,12 @@ static int check_unaligned_access_boot_cpu(void)
+
+ arch_initcall(check_unaligned_access_boot_cpu);
+
++void riscv_user_isa_enable(void)
++{
++ if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
++ csr_set(CSR_SENVCFG, ENVCFG_CBZE);
++}
++
+ #ifdef CONFIG_RISCV_ALTERNATIVE
+ /*
+ * Alternative patch sites consider 48 bits when determining when to patch
+diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
+index ff802d100a571..89ff6395dadbc 100644
+--- a/arch/riscv/kernel/setup.c
++++ b/arch/riscv/kernel/setup.c
+@@ -26,6 +26,7 @@
+ #include <asm/acpi.h>
+ #include <asm/alternative.h>
+ #include <asm/cacheflush.h>
++#include <asm/cpufeature.h>
+ #include <asm/cpu_ops.h>
+ #include <asm/early_ioremap.h>
+ #include <asm/pgtable.h>
+@@ -307,10 +308,13 @@ void __init setup_arch(char **cmdline_p)
+ riscv_fill_hwcap();
+ init_rt_signal_env();
+ apply_boot_alternatives();
++
+ if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
+ riscv_isa_extension_available(NULL, ZICBOM))
+ riscv_noncoherent_supported();
+ riscv_set_dma_cache_alignment();
++
++ riscv_user_isa_enable();
+ }
+
+ static int __init topology_init(void)
+diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
+index 1b8da4e40a4d6..d1b0a6fc3adfc 100644
+--- a/arch/riscv/kernel/smpboot.c
++++ b/arch/riscv/kernel/smpboot.c
+@@ -25,6 +25,8 @@
+ #include <linux/of.h>
+ #include <linux/sched/task_stack.h>
+ #include <linux/sched/mm.h>
++
++#include <asm/cpufeature.h>
+ #include <asm/cpu_ops.h>
+ #include <asm/cpufeature.h>
+ #include <asm/irq.h>
+@@ -253,6 +255,8 @@ asmlinkage __visible void smp_callin(void)
+ elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
+ }
+
++ riscv_user_isa_enable();
++
+ /*
+ * Remote TLB flushes are ignored while the CPU is offline, so emit
+ * a local TLB flush right now just in case.
+--
+2.39.5
+
--- /dev/null
+From 6f33157c34e73fbf4c18354a08227be730608e27 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Jun 2024 21:14:24 +0800
+Subject: riscv: cacheinfo: initialize cacheinfo's level and type from ACPI
+ PPTT
+
+From: Yunhui Cui <cuiyunhui@bytedance.com>
+
+[ Upstream commit 604f32ea6909b0ebb8ab0bf1ab7dc66ee3dc8955 ]
+
+Before cacheinfo can be built correctly, we need to initialize level
+and type. Since RISC-V currently does not have a register group that
+describes cache-related attributes like ARM64, we cannot obtain them
+directly, so now we obtain cache leaves from the ACPI PPTT table
+(acpi_get_cache_info()) and set the cache type through split_levels.
+
+Suggested-by: Jeremy Linton <jeremy.linton@arm.com>
+Suggested-by: Sudeep Holla <sudeep.holla@arm.com>
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
+Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
+Link: https://lore.kernel.org/r/20240617131425.7526-2-cuiyunhui@bytedance.com
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index 30a6878287ad4..d6c108c50cba9 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -3,6 +3,7 @@
+ * Copyright (C) 2017 SiFive
+ */
+
++#include <linux/acpi.h>
+ #include <linux/cpu.h>
+ #include <linux/of.h>
+ #include <asm/cacheinfo.h>
+@@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
+ struct device_node *prev = NULL;
+ int levels = 1, level = 1;
+
++ if (!acpi_disabled) {
++ int ret, fw_levels, split_levels;
++
++ ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
++ if (ret)
++ return ret;
++
++ BUG_ON((split_levels > fw_levels) ||
++ (split_levels + fw_levels > this_cpu_ci->num_leaves));
++
++ for (; level <= this_cpu_ci->num_levels; level++) {
++ if (level <= split_levels) {
++ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
++ } else {
++ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
++ }
++ }
++ return 0;
++ }
++
+ if (of_property_read_bool(np, "cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+ if (of_property_read_bool(np, "i-cache-size"))
+--
+2.39.5
+
--- /dev/null
+From 4bb1b23b69b47af9289d9e8ca3d26b6b184612ab Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Jun 2024 21:14:23 +0800
+Subject: riscv: cacheinfo: remove the useless input parameter (node) of
+ ci_leaf_init()
+
+From: Yunhui Cui <cuiyunhui@bytedance.com>
+
+[ Upstream commit ee3fab10cb1566562aa683f319066eaeecccf918 ]
+
+ci_leaf_init() is a declared static function. The implementation of the
+function body and the caller do not use the parameter (struct device_node
+*node) input parameter, so remove it.
+
+Fixes: 6a24915145c9 ("Revert "riscv: Set more data to cacheinfo"")
+Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
+Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Link: https://lore.kernel.org/r/20240617131425.7526-1-cuiyunhui@bytedance.com
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/kernel/cacheinfo.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index 09e9b88110d15..30a6878287ad4 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -64,7 +64,6 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type)
+ }
+
+ static void ci_leaf_init(struct cacheinfo *this_leaf,
+- struct device_node *node,
+ enum cache_type type, unsigned int level)
+ {
+ this_leaf->level = level;
+@@ -80,11 +79,11 @@ int populate_cache_leaves(unsigned int cpu)
+ int levels = 1, level = 1;
+
+ if (of_property_read_bool(np, "cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+ if (of_property_read_bool(np, "i-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+ if (of_property_read_bool(np, "d-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+
+ prev = np;
+ while ((np = of_find_next_cache_node(np))) {
+@@ -97,11 +96,11 @@ int populate_cache_leaves(unsigned int cpu)
+ if (level <= levels)
+ break;
+ if (of_property_read_bool(np, "cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+ if (of_property_read_bool(np, "i-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+ if (of_property_read_bool(np, "d-cache-size"))
+- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
++ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+ levels = level;
+ }
+ of_node_put(np);
+--
+2.39.5
+
--- /dev/null
+From add25c11d8d5723f0758897621e3351ffc6ab8db Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 4 Nov 2024 13:03:13 -0600
+Subject: riscv: cacheinfo: Use of_property_present() for non-boolean
+ properties
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Rob Herring <robh@kernel.org>
+
+[ Upstream commit fb8179ce2996bffaa36a04e2b6262843b01b7565 ]
+
+The use of of_property_read_bool() for non-boolean properties is
+deprecated in favor of of_property_present() when testing for property
+presence.
+
+Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
+Reviewed-by: Clément Léger <cleger@rivosinc.com>
+Cc: stable@vger.kernel.org
+Fixes: 76d2a0493a17 ("RISC-V: Init and Halt Code")
+Link: https://lore.kernel.org/r/20241104190314.270095-1-robh@kernel.org
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/kernel/cacheinfo.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index d32dfdba083e1..9fb97c9f9b0be 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -103,11 +103,11 @@ int populate_cache_leaves(unsigned int cpu)
+ if (!np)
+ return -ENOENT;
+
+- if (of_property_read_bool(np, "cache-size"))
++ if (of_property_present(np, "cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+- if (of_property_read_bool(np, "i-cache-size"))
++ if (of_property_present(np, "i-cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+- if (of_property_read_bool(np, "d-cache-size"))
++ if (of_property_present(np, "d-cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+
+ prev = np;
+@@ -120,11 +120,11 @@ int populate_cache_leaves(unsigned int cpu)
+ break;
+ if (level <= levels)
+ break;
+- if (of_property_read_bool(np, "cache-size"))
++ if (of_property_present(np, "cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+- if (of_property_read_bool(np, "i-cache-size"))
++ if (of_property_present(np, "i-cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+- if (of_property_read_bool(np, "d-cache-size"))
++ if (of_property_present(np, "d-cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+ levels = level;
+ }
+--
+2.39.5
+
--- /dev/null
+From bad8ee979058d5d23e744e9278ea3561eee9a64a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 13 Sep 2024 10:00:52 +0200
+Subject: riscv: Prevent a bad reference count on CPU nodes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Miquel Sabaté Solà <mikisabate@gmail.com>
+
+[ Upstream commit 37233169a6ea912020c572f870075a63293b786a ]
+
+When populating cache leaves we previously fetched the CPU device node
+at the very beginning. But when ACPI is enabled we go through a
+specific branch which returns early and does not call 'of_node_put' for
+the node that was acquired.
+
+Since we are not using a CPU device node for the ACPI code anyways, we
+can simply move the initialization of it just passed the ACPI block, and
+we are guaranteed to have an 'of_node_put' call for the acquired node.
+This prevents a bad reference count of the CPU device node.
+
+Moreover, the previous function did not check for errors when acquiring
+the device node, so a return -ENOENT has been added for that case.
+
+Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
+Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
+Fixes: 604f32ea6909 ("riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT")
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/r/20240913080053.36636-1-mikisabate@gmail.com
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/kernel/cacheinfo.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
+index d6c108c50cba9..d32dfdba083e1 100644
+--- a/arch/riscv/kernel/cacheinfo.c
++++ b/arch/riscv/kernel/cacheinfo.c
+@@ -75,8 +75,7 @@ int populate_cache_leaves(unsigned int cpu)
+ {
+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+ struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+- struct device_node *np = of_cpu_device_node_get(cpu);
+- struct device_node *prev = NULL;
++ struct device_node *np, *prev;
+ int levels = 1, level = 1;
+
+ if (!acpi_disabled) {
+@@ -100,6 +99,10 @@ int populate_cache_leaves(unsigned int cpu)
+ return 0;
+ }
+
++ np = of_cpu_device_node_get(cpu);
++ if (!np)
++ return -ENOENT;
++
+ if (of_property_read_bool(np, "cache-size"))
+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+ if (of_property_read_bool(np, "i-cache-size"))
+--
+2.39.5
+
--- /dev/null
+From 6173dfaba0bf31bccb417c749342119655314f76 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 20 Dec 2024 16:39:24 +0800
+Subject: riscv: signal: fix signal_minsigstksz
+
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
+
+[ Upstream commit 564fc8eb6f78e01292ff10801f318feae6153fdd ]
+
+The init_rt_signal_env() funciton is called before the alternative patch
+is applied, so using the alternative-related API to check the availability
+of an extension within this function doesn't have the intended effect.
+This patch reorders the init_rt_signal_env() and apply_boot_alternatives()
+to get the correct signal_minsigstksz.
+
+Fixes: e92f469b0771 ("riscv: signal: Report signal frame size to userspace via auxv")
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
+Reviewed-by: Zong Li <zong.li@sifive.com>
+Reviewed-by: Andy Chiu <andybnac@gmail.com>
+Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/r/20241220083926.19453-3-yongxuan.wang@sifive.com
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/riscv/kernel/setup.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
+index 89ff6395dadbc..175184b059264 100644
+--- a/arch/riscv/kernel/setup.c
++++ b/arch/riscv/kernel/setup.c
+@@ -306,8 +306,8 @@ void __init setup_arch(char **cmdline_p)
+
+ riscv_init_cbo_blocksizes();
+ riscv_fill_hwcap();
+- init_rt_signal_env();
+ apply_boot_alternatives();
++ init_rt_signal_env();
+
+ if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
+ riscv_isa_extension_available(NULL, ZICBOM))
+--
+2.39.5
+
--- /dev/null
+drm-i915-xe2lpd-move-d2d-enable-disable.patch
+drm-i915-ddi-fix-hdmi-port-width-programming-in-ddi_.patch
+arm64-dts-rockchip-add-rs485-support-on-uart5-of-px3.patch
+smb-client-fix-chmod-2-regression-with-attr_readonly.patch
+ibmvnic-perform-tx-cso-during-send-scrq-direct.patch
+ibmvnic-inspect-header-requirements-before-using-scr.patch
+drm-amdgpu-check-extended-configuration-space-regist.patch
+drm-amdgpu-disable-bar-resize-on-dell-g5-se.patch
+net-enetc-remove-setting-of-rx-software-timestamp.patch
+net-enetc-replace-ifdef-with-is_enabled.patch
+net-enetc-vfs-do-not-support-hwtstamp_tx_onestep_syn.patch
+x86-speculation-add-__update_spec_ctrl-helper.patch
+nfs-o_direct-writes-must-check-and-adjust-the-file-l.patch
+riscv-cacheinfo-remove-the-useless-input-parameter-n.patch
+riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch
+riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch
+riscv-cacheinfo-use-of_property_present-for-non-bool.patch
+risc-v-enable-cbo.zero-in-usermode.patch
+riscv-signal-fix-signal_minsigstksz.patch
+efi-don-t-map-the-entire-mokvar-table-to-determine-i.patch
--- /dev/null
+From 154e083ed7e08fd6dfe0536abdcf223519dd652a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 16 Feb 2025 18:02:47 -0300
+Subject: smb: client: fix chmod(2) regression with ATTR_READONLY
+
+From: Paulo Alcantara <pc@manguebit.com>
+
+[ Upstream commit 654292a0b264e9b8c51b98394146218a21612aa1 ]
+
+When the user sets a file or directory as read-only (e.g. ~S_IWUGO),
+the client will set the ATTR_READONLY attribute by sending an
+SMB2_SET_INFO request to the server in cifs_setattr_{,nounix}(), but
+cifsInodeInfo::cifsAttrs will be left unchanged as the client will
+only update the new file attributes in the next call to
+{smb311_posix,cifs}_get_inode_info() with the new metadata filled in
+@data parameter.
+
+Commit a18280e7fdea ("smb: cilent: set reparse mount points as
+automounts") mistakenly removed the @data NULL check when calling
+is_inode_cache_good(), which broke the above case as the new
+ATTR_READONLY attribute would end up not being updated on files with a
+read lease.
+
+Fix this by updating the inode whenever we have cached metadata in
+@data parameter.
+
+Reported-by: Horst Reiterer <horst.reiterer@fabasoft.com>
+Closes: https://lore.kernel.org/r/85a16504e09147a195ac0aac1c801280@fabasoft.com
+Fixes: a18280e7fdea ("smb: cilent: set reparse mount points as automounts")
+Cc: stable@vger.kernel.org
+Signed-off-by: Paulo Alcantara (Red Hat) <pc@manguebit.com>
+Signed-off-by: Steve French <stfrench@microsoft.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/smb/client/inode.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/fs/smb/client/inode.c b/fs/smb/client/inode.c
+index b3e59a7c71205..dbb407d5e6dab 100644
+--- a/fs/smb/client/inode.c
++++ b/fs/smb/client/inode.c
+@@ -1320,7 +1320,7 @@ int cifs_get_inode_info(struct inode **inode,
+ struct cifs_fattr fattr = {};
+ int rc;
+
+- if (is_inode_cache_good(*inode)) {
++ if (!data && is_inode_cache_good(*inode)) {
+ cifs_dbg(FYI, "No need to revalidate cached inode sizes\n");
+ return 0;
+ }
+@@ -1419,7 +1419,7 @@ int smb311_posix_get_inode_info(struct inode **inode,
+ struct cifs_fattr fattr = {};
+ int rc;
+
+- if (is_inode_cache_good(*inode)) {
++ if (!data && is_inode_cache_good(*inode)) {
+ cifs_dbg(FYI, "No need to revalidate cached inode sizes\n");
+ return 0;
+ }
+--
+2.39.5
+
--- /dev/null
+From 2a1137eb2a6dfc6b4c27569508736706b66b156f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 27 Jul 2023 14:45:57 -0400
+Subject: x86/speculation: Add __update_spec_ctrl() helper
+
+From: Waiman Long <longman@redhat.com>
+
+[ Upstream commit e3e3bab1844d448a239cd57ebf618839e26b4157 ]
+
+Add a new __update_spec_ctrl() helper which is a variant of
+update_spec_ctrl() that can be used in a noinstr function.
+
+Suggested-by: Peter Zijlstra <peterz@infradead.org>
+Signed-off-by: Waiman Long <longman@redhat.com>
+Signed-off-by: Ingo Molnar <mingo@kernel.org>
+Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Cc: Linus Torvalds <torvalds@linux-foundation.org>
+Link: https://lore.kernel.org/r/20230727184600.26768-2-longman@redhat.com
+Stable-dep-of: c157d351460b ("intel_idle: Handle older CPUs, which stop the TSC in deeper C states, correctly")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/include/asm/spec-ctrl.h | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/x86/include/asm/spec-ctrl.h b/arch/x86/include/asm/spec-ctrl.h
+index cb0386fc4dc3b..c648502e45357 100644
+--- a/arch/x86/include/asm/spec-ctrl.h
++++ b/arch/x86/include/asm/spec-ctrl.h
+@@ -4,6 +4,7 @@
+
+ #include <linux/thread_info.h>
+ #include <asm/nospec-branch.h>
++#include <asm/msr.h>
+
+ /*
+ * On VMENTER we must preserve whatever view of the SPEC_CTRL MSR
+@@ -76,6 +77,16 @@ static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)
+ return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL;
+ }
+
++/*
++ * This can be used in noinstr functions & should only be called in bare
++ * metal context.
++ */
++static __always_inline void __update_spec_ctrl(u64 val)
++{
++ __this_cpu_write(x86_spec_ctrl_current, val);
++ native_wrmsrl(MSR_IA32_SPEC_CTRL, val);
++}
++
+ #ifdef CONFIG_SMP
+ extern void speculative_store_bypass_ht_init(void);
+ #else
+--
+2.39.5
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
