arm64: dts: renesas: rcar-gen3: Increase CANFD clock rates

Currently, all R-Car Gen3 .dtsi files configure the CANFD core clocks to
40 MHz, which limits CAN-FD data transfer rates to 4 Mbps.  However, all
R-Car Gen3 SoCs except for R-Car D3 support CANFD clock rates up to 80
MHz.

Now the R-Car CAN-FD driver has gained support for Transceiver Delay
Compensation, increase all appropriate CANFD clock rates to the
documented maximum, to support data rates up to 8 Mbps.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/d1ca3cd184193084b6de4332d47d0aee1923f6a6.1755090456.git.geert+renesas@glider.be

diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
index 6ee9cdeb5a3ab478d70c1ad2558a6064f3314329..c389ebc7e6ce8f00c4371c30e3b8dbffd44b34fc 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
@@ -1373,7 +1373,7 @@
                               <&can_clk>;
                        clock-names = "fck", "canfd", "can_clk";
                        assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
-                       assigned-clock-rates = <40000000>;
+                       assigned-clock-rates = <80000000>;
                        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
                        resets = <&cpg 914>;
                        status = "disabled";

diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
index a323ac47ca70f3dbd90b23422262f161189f4f0e..6d039019905ded0a460e5b5e9e41a391d8b00672 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
@@ -1245,7 +1245,7 @@
                               <&can_clk>;
                        clock-names = "fck", "canfd", "can_clk";
                        assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
-                       assigned-clock-rates = <40000000>;
+                       assigned-clock-rates = <80000000>;
                        power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
                        resets = <&cpg 914>;
                        status = "disabled";

diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
index 49f6d31c5903b8b3c313be03fcca47cfe9f22275..1637b534fc68b19dc8ab615ea692b9b8aec23474 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
@@ -1245,7 +1245,7 @@
                               <&can_clk>;
                        clock-names = "fck", "canfd", "can_clk";
                        assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
-                       assigned-clock-rates = <40000000>;
+                       assigned-clock-rates = <80000000>;
                        power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
                        resets = <&cpg 914>;
                        status = "disabled";

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 136a22ca50b7867426fc9f5a6fe95c4b45703da4..353a77187089399440bf82b8c00b460d572ec4a0 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1108,7 +1108,7 @@
                               <&can_clk>;
                        clock-names = "fck", "canfd", "can_clk";
                        assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
-                       assigned-clock-rates = <40000000>;
+                       assigned-clock-rates = <80000000>;
                        power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
                        resets = <&cpg 914>;
                        status = "disabled";

diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 01744496805c3200a28303335369a497baeabab3..e7a5800bf74216faf76d177b60760cbdfad7220f 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -568,7 +568,7 @@
                                 <&can_clk>;
                        clock-names = "fck", "canfd", "can_clk";
                        assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>;
-                       assigned-clock-rates = <40000000>;
+                       assigned-clock-rates = <80000000>;
                        power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
                        resets = <&cpg 914>;
                        status = "disabled";

diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index f7e506ad7a211a57fc510f50b7c79f6e7065c123..964aa14f3e65d92515e1aeed16d904e0773c1ce9 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -621,7 +621,7 @@
                                 <&can_clk>;
                        clock-names = "fck", "canfd", "can_clk";
                        assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
-                       assigned-clock-rates = <40000000>;
+                       assigned-clock-rates = <80000000>;
                        power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
                        resets = <&cpg 914>;
                        status = "disabled";

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 6b8742045836b9b9638b07a1327b4fbcbbc2ede8..e16ede6eb3791ad182ac9a72087eef9670a594aa 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1061,7 +1061,7 @@
                               <&can_clk>;
                        clock-names = "fck", "canfd", "can_clk";
                        assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
-                       assigned-clock-rates = <40000000>;
+                       assigned-clock-rates = <80000000>;
                        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
                        resets = <&cpg 914>;
                        status = "disabled";