zynqmp: qspi: Add Dual parallel and Dual stacked support

Add qspi dual parallel and dual stacked support for zynqmp.
Determine qspi mode based on MIO settings.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile
index 53236db6b327054bd46052f3da43c02c8c1332fb..de770778d6ef90fe5ed5a7c31fb41ab432c2f109 100644 (file)
--- a/arch/arm/cpu/armv8/zynqmp/Makefile
+++ b/arch/arm/cpu/armv8/zynqmp/Makefile
@@ -7,3 +7,4 @@
 
 obj-y  += clk.o
 obj-y  += cpu.o
+obj-y  += slcr.o

diff --git a/arch/arm/cpu/armv8/zynqmp/slcr.c b/arch/arm/cpu/armv8/zynqmp/slcr.c
new file mode 100644 (file)
index 0000000..d1831e6
--- /dev/null
+++ b/arch/arm/cpu/armv8/zynqmp/slcr.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clk.h>
+
+#define SLCR_QSPI_ENABLE       0x02
+#define SLCR_QSPI_ENABLE_MASK  0x03
+
+/*
+ * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
+ *
+ * @peri_name: Name of the peripheral for checking MIO status
+ * @get_pins: Pointer to array of get pin for this peripheral
+ * @num_pins: Number of pins for this peripheral
+ * @mask: Mask value
+ * @check_val: Required check value to get the status of  periph
+ */
+struct zynq_slcr_mio_get_status {
+       const char *peri_name;
+       const int *get_pins;
+       int num_pins;
+       u32 mask;
+       u32 check_val;
+};
+
+static const int qspi0_pins[] = {
+       0, 1, 2, 3, 4, 5
+};
+
+static const int qspi1_cs_pin[] = {
+       7
+};
+
+static const int qspi1_pins[] = {
+       8, 9, 10, 11, 12
+};
+
+static const struct zynq_slcr_mio_get_status mio_periphs[] = {
+        {
+                "qspi0",
+                qspi0_pins,
+                ARRAY_SIZE(qspi0_pins),
+                SLCR_QSPI_ENABLE_MASK,
+                SLCR_QSPI_ENABLE,
+        },
+        {
+                "qspi1_cs",
+                qspi1_cs_pin,
+                ARRAY_SIZE(qspi1_cs_pin),
+                SLCR_QSPI_ENABLE_MASK,
+                SLCR_QSPI_ENABLE,
+        },
+        {
+                "qspi1",
+                qspi1_pins,
+                ARRAY_SIZE(qspi1_pins),
+                SLCR_QSPI_ENABLE_MASK,
+                SLCR_QSPI_ENABLE,
+        },
+};
+
+/*
+ * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
+ *
+ * @periph: Name of the peripheral
+ *
+ * Returns count to indicate the number of pins configured for the
+ * given @periph.
+ */
+int zynq_slcr_get_mio_pin_status(const char *periph)
+{
+       const struct zynq_slcr_mio_get_status *mio_ptr;
+       int val, i, j;
+       int mio = 0;
+
+       for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
+               if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
+                       mio_ptr = &mio_periphs[i];
+                       for (j = 0; j < mio_ptr->num_pins; j++) {
+                               val = readl(&slcr_base->mio_pin
+                                               [mio_ptr->get_pins[j]]);
+                               if ((val & mio_ptr->mask) == mio_ptr->check_val)
+                                       mio++;
+                       }
+                       break;
+               }
+       }
+
+       return mio;
+}

diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 827a530cb252acd925e00d823a9797bed79c06e1..c5611b3439a665d1598397f7e6f21e95da582ee2 100644 (file)
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -61,6 +61,15 @@ struct csu_regs {
 
 #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
 
+#define ZYNQMP_IOU_SLCR_BASEADDR       0xFF180000
+
+struct iou_slcr_regs {
+       u32 mio_pin[78];
+       u32 reserved[442];
+};
+
+#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
+
 /* Board version value */
 #define ZYNQMP_CSU_VERSION_SILICON     0x0
 #define ZYNQMP_CSU_VERSION_EP108       0x1

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index e28ac24dc18cf9619f8ab79cdbb15b825514f87e..6c1b1bab2493445dea1b1f3c8b8bb12f60a382c0 100644 (file)
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -833,7 +833,6 @@ static int zynq_qspi_check_is_dual_flash(void)
        int is_dual = -1;
        int lower_mio = 0, upper_mio = 0, upper_mio_cs1 = 0;
 
-#ifndef XILINX_ZYNQMP
        lower_mio = zynq_slcr_get_mio_pin_status("qspi0");
        if (lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0)
                is_dual = SF_SINGLE_FLASH;
@@ -848,9 +847,6 @@ static int zynq_qspi_check_is_dual_flash(void)
            (upper_mio_cs1 == ZYNQ_QSPI_MIO_NUM_QSPI1_CS) &&
            (upper_mio == ZYNQ_QSPI_MIO_NUM_QSPI1))
                is_dual = SF_DUAL_PARALLEL_FLASH;
-#else
-       is_dual = SF_SINGLE_FLASH;
-#endif
 
        return is_dual;
 }

diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 0f671b0cb9d1b561f2b89c36aa4d3a8c23b0c7c6..1d53273b45b54bfe9094da3c79030c8d2bb0fd73 100644 (file)
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -106,6 +106,7 @@
 # define CONFIG_SF_DEFAULT_SPEED        30000000
 # define CONFIG_SPI_FLASH
 # define CONFIG_SPI_FLASH_BAR
+# define CONFIG_SF_DUAL_FLASH
 # define CONFIG_SPI_FLASH_SPANSION
 # define CONFIG_SPI_FLASH_STMICRO
 # define CONFIG_SPI_FLASH_WINBOND