]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
5.15-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 10 Jan 2023 17:31:05 +0000 (18:31 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 10 Jan 2023 17:31:05 +0000 (18:31 +0100)
added patches:
drm-mgag200-fix-pll-setup-for-g200_se_a-rev-4.patch

queue-5.15/drm-mgag200-fix-pll-setup-for-g200_se_a-rev-4.patch [new file with mode: 0644]
queue-5.15/series

diff --git a/queue-5.15/drm-mgag200-fix-pll-setup-for-g200_se_a-rev-4.patch b/queue-5.15/drm-mgag200-fix-pll-setup-for-g200_se_a-rev-4.patch
new file mode 100644 (file)
index 0000000..694998c
--- /dev/null
@@ -0,0 +1,45 @@
+From b389286d0234e1edbaf62ed8bc0892a568c33662 Mon Sep 17 00:00:00 2001
+From: Jocelyn Falempe <jfalempe@redhat.com>
+Date: Thu, 13 Oct 2022 15:28:10 +0200
+Subject: drm/mgag200: Fix PLL setup for G200_SE_A rev >=4
+
+From: Jocelyn Falempe <jfalempe@redhat.com>
+
+commit b389286d0234e1edbaf62ed8bc0892a568c33662 upstream.
+
+For G200_SE_A, PLL M setting is wrong, which leads to blank screen,
+or "signal out of range" on VGA display.
+previous code had "m |= 0x80" which was changed to
+m |= ((pixpllcn & BIT(8)) >> 1);
+
+Tested on G200_SE_A rev 42
+
+This line of code was moved to another file with
+commit 877507bb954e ("drm/mgag200: Provide per-device callbacks for
+PIXPLLC") but can be easily backported before this commit.
+
+v2: * put BIT(7) First to respect MSB-to-LSB (Thomas)
+    * Add a comment to explain that this bit must be set (Thomas)
+
+Fixes: 2dd040946ecf ("drm/mgag200: Store values (not bits) in struct mgag200_pll_values")
+Cc: stable@vger.kernel.org
+Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
+Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/20221013132810.521945-1-jfalempe@redhat.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/mgag200/mgag200_pll.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/mgag200/mgag200_pll.c
++++ b/drivers/gpu/drm/mgag200/mgag200_pll.c
+@@ -268,7 +268,8 @@ static void mgag200_pixpll_update_g200se
+       pixpllcp = pixpllc->p - 1;
+       pixpllcs = pixpllc->s;
+-      xpixpllcm = pixpllcm | ((pixpllcn & BIT(8)) >> 1);
++      // For G200SE A, BIT(7) should be set unconditionally.
++      xpixpllcm = BIT(7) | pixpllcm;
+       xpixpllcn = pixpllcn;
+       xpixpllcp = (pixpllcs << 3) | pixpllcp;
index 4d6e16e9c356befe0099dfc68bcfacf48f4d3b9f..d220e82a1fd242b8857951a2b130bdb28f6a8a75 100644 (file)
@@ -287,3 +287,4 @@ net-hns3-fix-return-value-check-bug-of-rx-copybreak.patch
 mbcache-avoid-nesting-of-cache-c_list_lock-under-bit-locks.patch
 efi-random-combine-bootloader-provided-rng-seed-with-rng-protocol-output.patch
 io_uring-fix-unsigned-res-comparison-with-zero-in-io_fixup_rw_res.patch
+drm-mgag200-fix-pll-setup-for-g200_se_a-rev-4.patch