RISC-V: Remove unnecessary asm check for binop constraint

The vsetvl asm check is unnecessary for the binop constraint. We
should be focus for constrait and leave the vsetvl test to the
vsetvl pass.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/binop_vv_constraint-1.c: Remove the
	vsetvl asm check from func body.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-1.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-10.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-11.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-129.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-13.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-130.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-131.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-133.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-134.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-135.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-14.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-15.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-153.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-154.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-155.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-158.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-171.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-172.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-173.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-174.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-18.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-2.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-20.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-22.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-24.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-26.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-28.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-3.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-30.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-32.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-34.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-36.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-37.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-38.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-39.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-41.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-42.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-43.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-5.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-6.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-7.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-9.c: Ditto.
	* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto.
	* gcc.target/riscv/rvv/base/ternop_vv_constraint-1.c: Ditto.
	* gcc.target/riscv/rvv/base/ternop_vv_constraint-2.c: Ditto.
	* gcc.target/riscv/rvv/base/ternop_vv_constraint-3.c: Ditto.
	* gcc.target/riscv/rvv/base/ternop_vv_constraint-4.c: Ditto.
	* gcc.target/riscv/rvv/base/ternop_vv_constraint-5.c: Ditto.
	* gcc.target/riscv/rvv/base/ternop_vv_constraint-6.c: Ditto.
	* gcc.target/riscv/rvv/base/ternop_vx_constraint-1.c: Ditto.
	* gcc.target/riscv/rvv/base/ternop_vx_constraint-8.c: Ditto.
	* gcc.target/riscv/rvv/base/ternop_vx_constraint-9.c: Ditto.
	* gcc.target/riscv/rvv/base/unop_v_constraint-1.c: Ditto.
	* gcc.target/riscv/rvv/base/unop_v_constraint-2.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c
index 3372ec1d2306e57fc0f2bff4939538d9cc5cdda7..4fc7f40829123c5d84688c832726385a21bef5f0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 **     vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 **     vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-1.c
index 09e0e21925b58cf47d6fc0a93f95c983228aee86..9a248bfa6131f682035e8bb7756b42dd6e51674e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-10.c
index faf5ffb47f1a986188d040209a27d14fcf33ad31..c40d6765f27a07d7811c1a40b61ec22f4ce81f49 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-10.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-11.c
index 54fe941f6ad1b326af1c10794c120063637418cb..b9b09a8b67f729654c38b87926c9a307dd3e6927 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-11.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
index 8a18a1df53567bf600b0d74930b60c56f23ee1b2..634c12a4c0e7100efa618fb06d2b386bb90dbfed 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c
index db5dfe1fc3e838f07362045bf120843c6fba09e5..b99628bf12b8b6c70ca6a0f34da967b18ea52224 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+** ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+** ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+** ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+** ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+** ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-13.c
index d844e1baf2fc46bcd898dfaed93d5b180244eca2..4d8e641e1b752e1a468f40b08c4f477a2912f110 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-13.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c
index da6b02ddd2df15f1161dd925b91ec35b2eb1bc4e..47c984b8a0bf8b12ab09ca5a718e821211d1e901 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+** ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+** ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+** ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+** ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+** ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c
index 16d35c8053d8cc796a3888848a584244aadd6649..b6e12b3a9c8283e0139911cc1a30239102831860 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c
index 2da8ab7c15e35a1b543d557beeb6f98b536f8aa6..f6d0d7fb31d82c0eb9e482ec9c883ff0a16e66b6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c
index a83fee484949392b6e4d0d5f3f804c691118ff11..ff39b24e3e01d046a245ea3f687861fd6ce95a1c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c
index 767987657b97495e3a9d46f712328292c8f35269..4852601cd1ca7fc7a201ef8052eef536b1fde8f9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-14.c
index 6779dfe859a166325c4b80988b99799306185ae7..4c07a334611af25e27c479a01704b05ac4627ae5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-14.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-15.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-15.c
index 611a86f2b1596977714f3ad3335e2e0de7f7f411..82cc944ad310147cb0a5d0c74c3c66b6c12f30eb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-15.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c
index a941bcd31819cc2c01293a923b70fea6da99c990..a0f6c676d8873f75001037bde01255682d59d642 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -26,9 +26,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -51,9 +51,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c
index ddbde574565f1de6e4f6f18f77fb6acd8344159c..8e18d763504963e947266707873a2dfc1b32804f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c
index d22f3e4baa69ed3e40ff23d1b821f271b83ad02b..4b5e68118efe1c519ff442f9e667e8320e6727ee 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c
index d22f3e4baa69ed3e40ff23d1b821f271b83ad02b..4b5e68118efe1c519ff442f9e667e8320e6727ee 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
index 0a7a1e88391269a23037f90ca094867850cb2c78..651d61001c1423aea76a41a9448f6d72c0796827 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
index eeea3517e01fe8a6e24c3255cea402a72161bbf8..d19a9fda23562979e01ee77d0d58d2ef3be601a2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c
index 6e8669ae59ec5532c42f037b50a28d17475ac4bf..591a99e4e1cedf7f4993a2a3cc7b4a8ec7012c0f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c
@@ -7,10 +7,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au]
-**  ...
-**     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
-**  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -41,10 +37,6 @@ void f1 (void * in, void *out, int64_t x, int n)
 /*
 ** f2:
 **  ...
-**     vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au]
-**  ...
-**     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
-**  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-172.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-172.c
index 060c853a698896c1349606d3d5ebb3ed4090bd46..ae48b085084b53f7bf5edf5da7d309edcbb4e6cd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-172.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-172.c
@@ -7,8 +7,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,\s*4,e32,m1,tu,m[au]
-**  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -39,8 +37,6 @@ void f1 (void * in, void *out, int64_t x, int n)
 /*
 ** f2:
 **  ...
-**     vsetivli\tzero,\s*4,e32,m1,tu,m[au]
-**  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c
index af9c45e942b499688bbbb7622bc8b3a1fa71c17d..ca68cc5b6184b503030bacd1582975df0dc3e0d8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c
@@ -7,10 +7,6 @@
 /*
 ** f1:
 **  ...
-**     vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au]
-**  ...
-**     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
-**  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -41,10 +37,6 @@ void f1 (void * in, void *out, int64_t x, int vl)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au]
-**  ...
-**     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
-**  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-174.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-174.c
index f2e5d40ceb790f8606588eac51f1a162ecb310d1..c566db4dce7105c2ff24f367be796cf3156965eb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-174.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-174.c
@@ -7,8 +7,6 @@
 /*
 ** f1:
 **  ...
-**     vsetvli\t[a-x0-9]+,\s*zero,e32,m1,tu,m[au]
-**  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -39,8 +37,6 @@ void f1 (void * in, void *out, int64_t x, int vl)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,\s*zero,e32,m1,tu,m[au]
-**  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-18.c
index 328564fb0299968a525eb9f9127dc70b8b918634..db8960074e68d33cac9ff190b34e5ef0b064d26e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-18.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
index f4616b4c72b2776fb3a3e8661ce573656025fe48..16f431542d8f7c216a642c0e558a107ba538e61a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-2.c
index 2c02c35ef5756b60c4255af4b970e0056183e2c7..9c40181bf7cb24e45ce87d870ba55cee2312b73b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-2.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-20.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-20.c
index 441573623ab9843242dfd0c40676d75ffec7414a..d5c1dcfed3b1e97ad808a5159bb57f1213bb5cd1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-20.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
index c082f4059c3126ed229caaf2b725ba2a0855c7c0..347c846dcbbc01085b68f79b63cb329962938f57 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-22.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-22.c
index b4813626fc1641b62539d6488417a06f941c5036..28a1bc1569d27000c0e523b064b161de868ffb66 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-22.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
index fd6fd6740cae8d1fca9b96053977c6ebd4f6172b..bc414440ba2916819e7ec9e3cd369925c9248c60 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-24.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-24.c
index d8ed5b186a42c95a296bb67559e9a7c7cc9b8c76..eb74df5cd5edda2bcc3cfe2dabe2ece911d5aa3b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-24.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
index 66891acc15a9a3bdbb18f0932cdc6d69d5e374b7..ce3f3af9c3d175fd5aa36b4775dbd963b64d7b08 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-26.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-26.c
index b70a1360b3cb70b38c126218e4e747c21bc6def8..9b578cc7ac7b8be7b44b1f6a6a1918151847563d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-26.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
index 6f068296e5a36c364c0f6fc3327af2f10a20eb87..4946f84b916274240f77ad5bad9f1a46e59c0af5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-28.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-28.c
index a239a3380bc359c70fc6855d994467b1c80d0862..b1ca4cb8505916c4b284a621e8e2013cc0075f39 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-28.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
index 9424a46457e794da09d170f51ff7bf732fafa658..5f2eede0422150607a838b132f506b88975da89e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-3.c
index 1da0cb6e5ae5cde0185493d0e5d0d67d83a6c976..21c1fc5a89a657b4ed7849b41d41b1ff54b950bd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-3.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-30.c
index 272c0eab273b6c6622e382df9a052ab8e6ea8e30..a9ac723a5a235c444cc63ab06c0768fdb0d83058 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-30.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
index 9424a46457e794da09d170f51ff7bf732fafa658..5f2eede0422150607a838b132f506b88975da89e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-32.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-32.c
index 272c0eab273b6c6622e382df9a052ab8e6ea8e30..a9ac723a5a235c444cc63ab06c0768fdb0d83058 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-32.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
index 6f2bca4b58f8d4129ac7db8f0688e1a3b2d87a69..88fcba60345e2544a0da78f396738fec6d4cda22 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-34.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-34.c
index 45015d77d2dc248ecce6b10d780bbfc577d20b8c..edb35c89b6853d86f0d89dccc66b8a1833e1a7db 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-34.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
index 6f2bca4b58f8d4129ac7db8f0688e1a3b2d87a69..88fcba60345e2544a0da78f396738fec6d4cda22 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-36.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-36.c
index 45015d77d2dc248ecce6b10d780bbfc577d20b8c..edb35c89b6853d86f0d89dccc66b8a1833e1a7db 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-36.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-37.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-37.c
index 34de4458198a0d34e719da7ff465732fd2d30c5b..10322b6179023ad7c48a2d2cb85e487d3b736ab2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-37.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-38.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-38.c
index 1374becb8478f77175886e24111e01725f567db0..45452fe4597a4a435c1e947a896f049d3640b026 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-38.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-39.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-39.c
index 21b77b952e045ca7e79383edca81eed6dc4e7a21..ff470b37471c74f871ee2cf88d39080a6f6888f2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-39.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
index 297ed2384770e2d0195d99645a71bd87513da7fc..87a16453feabe310f9a488344ab1ffc683294889 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
index 653f043e47124d84564697ab5cc9109b9ecd7f29..c0321cefb9a6fff31d2480d231a9f329aa875e20 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-41.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-41.c
index 4ff352bd7afdbe873c6eb5963e8cf4b3293f6b72..7b6a1a853bac48eaadbd40aa08c3b8e38a59e9ea 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-41.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-41.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-42.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-42.c
index 975ebe709b913a18f4c21d10dca67ef907adb1a8..42f7ba4d0111d53fe23231f42aeb3bcaf0619438 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-42.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-42.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-43.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-43.c
index 4f3e9066f1629083fe41016410328544f3949181..555832986e52cfb1849c2ffbd2cd58dabbd6d8d0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-43.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-43.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
index d4dc4e0fe6ce1f8a4b1a8b30d109094c03315d6a..ab0f13ba255e3e93019a96bda1f3075d9d07b8c2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-5.c
index 29eab66774e57d14fee3c0da032757bd0072c988..0600f9858943118591a3d74accfc79a13c8ab05c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-5.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vxor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vxor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-6.c
index 67fd655ece2eaab3bbbfa52b01b747d4d707603f..dae7aaac2f8477a52234463094c6b88e3285b5c8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-6.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-7.c
index 71a320a161988aa55687bc2de74573cc237f73b0..8b80a7f5450ee90e6976b88c72f330948ec9d7a7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-7.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
index 797abbd2cc0518a9e508ba76551630acfa0805f1..9bf9ff59de7ad78ee06b078bd38fd73d196487de 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-9.c
index ce786e15244cda5dc4d14f2163bf1838b616f725..e92fe0c2d86c3bee0af6d5be899e7f5be7f8d826 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-9.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
index e40e193220c3311d5411c32200117937ba60449a..250e017cc8625561366caff3812ac636d070b5a1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsll\.vi\tv[0-9]+,\s*v[0-9]+,31
@@ -24,10 +24,9 @@ void f1 (void * in, void *out)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
 **     ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -48,9 +47,9 @@ void f2 (void * in, void *out)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17
@@ -71,7 +70,7 @@ void f3 (void * in, void *out)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -90,9 +89,9 @@ void f4 (void * in, void *out, size_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5
 **     vsll\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*5,\s*v0.t
@@ -112,9 +111,9 @@ void f5 (void * in, void *out)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-1.c
index 838776e5c507b7e055a9e5b93dfb71aa65f96191..7d0a44e43722f3df26159cc59a2ef67eb77c799f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-2.c
index 54506c1c9185a2a0f61bd4da6bd27a74f3d3fed5..61345f081b1ff86bf4cdac4e4ff7d3d9531fb811 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-2.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-3.c
index 5ff07da1146b7b9bf2e6c244cb0a2890a55372a1..100f12e1c2410bb8df76a23e2d4e6bbdbcc3fe99 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-3.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-4.c
index c280d97824ff22b2af1006e8c2175aa34d71c7f8..4dd09ae84b98268344132ef67052d1eeb48074e3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-4.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-5.c
index 1f71aa867c209e5b9eac8e9ba4370b0d660accba..02263b58cfdd391c99f26203766b6a33377c58b7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-5.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-6.c
index 2d2ed66143439302b0c1c2a33aa231b798b9c9df..db77dffba7b4de6ae7051e77858d13d589890875 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-6.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-1.c
index 90e120655d7b745b466804c456a665b2364feb3d..99083a479fb1b6f66bf0539048e04a6ea8b4c4b6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -47,9 +47,9 @@ void f2 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-8.c
index 82e14734056d7bbe8a7ba7e17b2b33a6f2491aac..6d0cd29cd06af3f013b62109f2c0a8a8bc2210b2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-8.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, float x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -47,9 +47,9 @@ void f2 (void * in, void * in2, void *out, float x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-9.c
index 1beed49d9ac2019c64874b5b96e5d4b67d72e809..db86eaabf16eee8e25bd32dece2dfeb62868c4d1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-9.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, float x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -47,9 +47,9 @@ void f2 (void * in, void * in2, void *out, float x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
index 1266784fd8f7bbb581ac2f47bcec39d3f674be55..64f4407d0b6e991163ad6913ddaae5757f4929fb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+
 **     vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+
 **     vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c
index 19f9365b42b5a526eec14c1aa5a96442d1dc9a70..3344d42352557e2570196a37c8f03f0a26c14eb5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+
@@ -24,12 +24,12 @@ void f1 (void * in, void *out)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+
-**     vsetvli\tzero,zero,e64,m2,ta,ma
+**  ...
 **     vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
 **     vse64\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ret
@@ -46,9 +46,9 @@ void f2 (void * in, void *out)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle16\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e16,mf4,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+
@@ -88,12 +88,12 @@ void f4 (void * in, void *out)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e16,mf4,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+
-**     vsetvli\tzero,zero,e32,mf2,ta,ma
+**  ...
 **     vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
 **     vse32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ret
@@ -110,9 +110,9 @@ void f5 (void * in, void *out)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e16,mf4,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+