dts: zynqmp: Update the OPPs for cpu freq

Update the points to operating-points-v2.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 2951cc5ae7171169502fb3bd1f542350895da30e..c44a6572745d1d0cfa72581095e84be32bc95702 100644 (file)
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -21,13 +21,7 @@
                        compatible = "arm,cortex-a53", "arm,armv8";
                        device_type = "cpu";
                        enable-method = "psci";
-                       operating-points = <
-                               /* kHz    uV */
-                               1100000  1000000
-                                550000  1000000
-                                366666  1000000
-                                275000  1000000
-                       >;
+                       operating-points-v2 = <&cpu_opp_table>;
                        reg = <0x0>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
                };
@@ -37,6 +31,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        reg = <0x1>;
+                       operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
                };
 
@@ -45,6 +40,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        reg = <0x2>;
+                       operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
                };
 
@@ -53,6 +49,7 @@
                        device_type = "cpu";
                        enable-method = "psci";
                        reg = <0x3>;
+                       operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
                };
 
@@ -70,6 +67,31 @@
                };
        };
 
+       cpu_opp_table: cpu_opp_table {
+               compatible = "operating-points-v2";
+               opp-shared;
+               opp00 {
+                       opp-hz = /bits/ 64 <1199999988>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <599999994>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <399999996>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <500000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <299999997>;
+                       opp-microvolt = <1000000>;
+                       clock-latency-ns = <500000>;
+               };
+       };
+
        dcc: dcc {
                compatible = "arm,dcc";
                status = "disabled";