Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
- drivers/media/i2c/smiapp/smiapp-core.c | 2 +-
+ drivers/media/i2c/smiapp/smiapp-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
-index 8b8ef6c6d48d4..2d77829b514de 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
-@@ -2764,7 +2764,7 @@ static int smiapp_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+@@ -2647,7 +2647,7 @@ static int smiapp_open(struct v4l2_subde
try_fmt->code = sensor->internal_csi_format->code;
try_fmt->field = V4L2_FIELD_NONE;
continue;
try_comp = v4l2_subdev_get_try_compose(sd, fh->pad, i);
---
-2.42.0
-
+++ /dev/null
-From d3a9fd04ac0887211b23ac4adf3d24d3c030fba4 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 21 Sep 2020 18:23:41 +0200
-Subject: media: i2c: smiapp: simplify getting state container
-
-From: Krzysztof Kozlowski <krzk@kernel.org>
-
-[ Upstream commit b5783c4d1fbeb2fc2d2fc8f2844e07eb65fb2cd3 ]
-
-The pointer to 'struct v4l2_subdev' is stored in drvdata via
-v4l2_i2c_subdev_init() so there is no point of a dance like:
-
- struct i2c_client *client = to_i2c_client(struct device *dev)
- struct v4l2_subdev *sd = i2c_get_clientdata(client);
-
-This allows to remove local variable 'client' and few pointer
-dereferences.
-
-Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
-Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
-Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-Stable-dep-of: 724ff68e968b ("media: ccs: Correctly initialise try compose rectangle")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/media/i2c/smiapp/smiapp-core.c | 28 ++++++++++++--------------
- 1 file changed, 13 insertions(+), 15 deletions(-)
-
-diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
-index 6fc0680a93d04..105ef29152e84 100644
---- a/drivers/media/i2c/smiapp/smiapp-core.c
-+++ b/drivers/media/i2c/smiapp/smiapp-core.c
-@@ -1185,8 +1185,7 @@ static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor)
-
- static int smiapp_power_on(struct device *dev)
- {
-- struct i2c_client *client = to_i2c_client(dev);
-- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
-+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- /*
- * The sub-device related to the I2C device is always the
-@@ -1199,14 +1198,14 @@ static int smiapp_power_on(struct device *dev)
-
- rval = regulator_enable(sensor->vana);
- if (rval) {
-- dev_err(&client->dev, "failed to enable vana regulator\n");
-+ dev_err(dev, "failed to enable vana regulator\n");
- return rval;
- }
- usleep_range(1000, 1000);
-
- rval = clk_prepare_enable(sensor->ext_clk);
- if (rval < 0) {
-- dev_dbg(&client->dev, "failed to enable xclk\n");
-+ dev_dbg(dev, "failed to enable xclk\n");
- goto out_xclk_fail;
- }
- usleep_range(1000, 1000);
-@@ -1230,7 +1229,7 @@ static int smiapp_power_on(struct device *dev)
- if (sensor->hwcfg->i2c_addr_alt) {
- rval = smiapp_change_cci_addr(sensor);
- if (rval) {
-- dev_err(&client->dev, "cci address change error\n");
-+ dev_err(dev, "cci address change error\n");
- goto out_cci_addr_fail;
- }
- }
-@@ -1238,14 +1237,14 @@ static int smiapp_power_on(struct device *dev)
- rval = smiapp_write(sensor, SMIAPP_REG_U8_SOFTWARE_RESET,
- SMIAPP_SOFTWARE_RESET);
- if (rval < 0) {
-- dev_err(&client->dev, "software reset failed\n");
-+ dev_err(dev, "software reset failed\n");
- goto out_cci_addr_fail;
- }
-
- if (sensor->hwcfg->i2c_addr_alt) {
- rval = smiapp_change_cci_addr(sensor);
- if (rval) {
-- dev_err(&client->dev, "cci address change error\n");
-+ dev_err(dev, "cci address change error\n");
- goto out_cci_addr_fail;
- }
- }
-@@ -1253,7 +1252,7 @@ static int smiapp_power_on(struct device *dev)
- rval = smiapp_write(sensor, SMIAPP_REG_U16_COMPRESSION_MODE,
- SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR);
- if (rval) {
-- dev_err(&client->dev, "compression mode set failed\n");
-+ dev_err(dev, "compression mode set failed\n");
- goto out_cci_addr_fail;
- }
-
-@@ -1261,28 +1260,28 @@ static int smiapp_power_on(struct device *dev)
- sensor, SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ,
- sensor->hwcfg->ext_clk / (1000000 / (1 << 8)));
- if (rval) {
-- dev_err(&client->dev, "extclk frequency set failed\n");
-+ dev_err(dev, "extclk frequency set failed\n");
- goto out_cci_addr_fail;
- }
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_LANE_MODE,
- sensor->hwcfg->lanes - 1);
- if (rval) {
-- dev_err(&client->dev, "csi lane mode set failed\n");
-+ dev_err(dev, "csi lane mode set failed\n");
- goto out_cci_addr_fail;
- }
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_FAST_STANDBY_CTRL,
- SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE);
- if (rval) {
-- dev_err(&client->dev, "fast standby set failed\n");
-+ dev_err(dev, "fast standby set failed\n");
- goto out_cci_addr_fail;
- }
-
- rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_SIGNALLING_MODE,
- sensor->hwcfg->csi_signalling_mode);
- if (rval) {
-- dev_err(&client->dev, "csi signalling mode set failed\n");
-+ dev_err(dev, "csi signalling mode set failed\n");
- goto out_cci_addr_fail;
- }
-
-@@ -1294,7 +1293,7 @@ static int smiapp_power_on(struct device *dev)
-
- rval = smiapp_call_quirk(sensor, post_poweron);
- if (rval) {
-- dev_err(&client->dev, "post_poweron quirks failed\n");
-+ dev_err(dev, "post_poweron quirks failed\n");
- goto out_cci_addr_fail;
- }
-
-@@ -1312,8 +1311,7 @@ static int smiapp_power_on(struct device *dev)
-
- static int smiapp_power_off(struct device *dev)
- {
-- struct i2c_client *client = to_i2c_client(dev);
-- struct v4l2_subdev *subdev = i2c_get_clientdata(client);
-+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
- struct smiapp_subdev *ssd = to_smiapp_subdev(subdev);
- struct smiapp_sensor *sensor =
- container_of(ssd, struct smiapp_sensor, ssds[0]);
---
-2.42.0
-
+++ /dev/null
-From 21d2748df5bd6a44dc5c8e88df0567d141f33bbc Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 3 Feb 2020 14:48:48 +0100
-Subject: media: smiapp: Add macros for accessing CCS registers
-
-From: Sakari Ailus <sakari.ailus@linux.intel.com>
-
-[ Upstream commit e66a7c84908688e99bd7da4a48bfcba1b292fe54 ]
-
-Add two helper macros for reading and writing the CCS registers as defined
-in ccs-regs.h.
-
-Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
-Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-Stable-dep-of: 724ff68e968b ("media: ccs: Correctly initialise try compose rectangle")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/media/i2c/smiapp/smiapp-regs.h | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h
-index 7223f5f891096..dc946096f3686 100644
---- a/drivers/media/i2c/smiapp/smiapp-regs.h
-+++ b/drivers/media/i2c/smiapp/smiapp-regs.h
-@@ -28,4 +28,10 @@ int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val);
-
- unsigned int ccs_reg_width(u32 reg);
-
-+#define ccs_read(sensor, reg_name, val) \
-+ smiapp_read(sensor, CCS_R_##reg_name, val)
-+
-+#define ccs_write(sensor, reg_name, val) \
-+ smiapp_write(sensor, CCS_R_##reg_name, val)
-+
- #endif
---
-2.42.0
-
+++ /dev/null
-From f7bc61fb8d08581534257dce1ad5542f7d244463 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 5 Feb 2020 15:21:06 +0100
-Subject: media: smiapp: Calculate CCS limit offsets and limit buffer size
-
-From: Sakari Ailus <sakari.ailus@linux.intel.com>
-
-[ Upstream commit ab47d5cd825310478900b33d712a0e39bf3bb716 ]
-
-Calculate the limit offsets and the size of the limit buffer. CCS limits
-are read into this buffer, and the offsets are helpful in accessing the
-information in it.
-
-Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
-Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-Stable-dep-of: 724ff68e968b ("media: ccs: Correctly initialise try compose rectangle")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/media/i2c/smiapp/Makefile | 2 +-
- drivers/media/i2c/smiapp/smiapp-core.c | 40 +++++++++++++++++++++++++-
- 2 files changed, 40 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile
-index 86f57a43f8e8b..efb643d2acace 100644
---- a/drivers/media/i2c/smiapp/Makefile
-+++ b/drivers/media/i2c/smiapp/Makefile
-@@ -1,6 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0-only
- smiapp-objs += smiapp-core.o smiapp-regs.o \
-- smiapp-quirk.o smiapp-limits.o
-+ smiapp-quirk.o smiapp-limits.o ccs-limits.o
- obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
-
- ccflags-y += -I $(srctree)/drivers/media/i2c
-diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
-index 105ef29152e84..75862e7647f87 100644
---- a/drivers/media/i2c/smiapp/smiapp-core.c
-+++ b/drivers/media/i2c/smiapp/smiapp-core.c
-@@ -27,6 +27,7 @@
- #include <media/v4l2-fwnode.h>
- #include <media/v4l2-device.h>
-
-+#include "ccs-limits.h"
- #include "smiapp.h"
-
- #define SMIAPP_ALIGN_DIM(dim, flags) \
-@@ -34,6 +35,11 @@
- ? ALIGN((dim), 2) \
- : (dim) & ~1)
-
-+static struct ccs_limit_offset {
-+ u16 lim;
-+ u16 info;
-+} ccs_limit_offsets[CCS_L_LAST + 1];
-+
- /*
- * smiapp_module_idents - supported camera modules
- */
-@@ -3166,7 +3172,39 @@ static struct i2c_driver smiapp_i2c_driver = {
- .id_table = smiapp_id_table,
- };
-
--module_i2c_driver(smiapp_i2c_driver);
-+static int smiapp_module_init(void)
-+{
-+ unsigned int i, l;
-+
-+ for (i = 0, l = 0; ccs_limits[i].size && l < CCS_L_LAST; i++) {
-+ if (!(ccs_limits[i].flags & CCS_L_FL_SAME_REG)) {
-+ ccs_limit_offsets[l + 1].lim =
-+ ALIGN(ccs_limit_offsets[l].lim +
-+ ccs_limits[i].size,
-+ ccs_reg_width(ccs_limits[i + 1].reg));
-+ ccs_limit_offsets[l].info = i;
-+ l++;
-+ } else {
-+ ccs_limit_offsets[l].lim += ccs_limits[i].size;
-+ }
-+ }
-+
-+ if (WARN_ON(ccs_limits[i].size))
-+ return -EINVAL;
-+
-+ if (WARN_ON(l != CCS_L_LAST))
-+ return -EINVAL;
-+
-+ return i2c_register_driver(THIS_MODULE, &smiapp_i2c_driver);
-+}
-+
-+static void smiapp_module_cleanup(void)
-+{
-+ i2c_del_driver(&smiapp_i2c_driver);
-+}
-+
-+module_init(smiapp_module_init);
-+module_exit(smiapp_module_cleanup);
-
- MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
- MODULE_DESCRIPTION("Generic SMIA/SMIA++ camera module driver");
---
-2.42.0
-
+++ /dev/null
-From ddd0987d1d1f12092ffe79de2fb85eb05fbedce1 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 22 Oct 2020 08:57:04 +0200
-Subject: media: smiapp: Import CCS definitions
-
-From: Sakari Ailus <sakari.ailus@linux.intel.com>
-
-[ Upstream commit 6493c4b777c2bca7fcfaabca2388d82f186f9be3 ]
-
-Import CCS register and limit definitions. These files are generated by a
-Perl script based on a text-based register definition file. The generator
-was added on
-commit 1ec0b899c2b7 ("media: ccs: Add the generator for CCS register definitions and limits")
-
-Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
-Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-Stable-dep-of: 724ff68e968b ("media: ccs: Correctly initialise try compose rectangle")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/media/i2c/smiapp/ccs-limits.c | 239 +++++++
- drivers/media/i2c/smiapp/ccs-limits.h | 259 +++++++
- drivers/media/i2c/smiapp/ccs-regs.h | 954 ++++++++++++++++++++++++++
- 3 files changed, 1452 insertions(+)
- create mode 100644 drivers/media/i2c/smiapp/ccs-limits.c
- create mode 100644 drivers/media/i2c/smiapp/ccs-limits.h
- create mode 100644 drivers/media/i2c/smiapp/ccs-regs.h
-
-diff --git a/drivers/media/i2c/smiapp/ccs-limits.c b/drivers/media/i2c/smiapp/ccs-limits.c
-new file mode 100644
-index 0000000000000..f5511789ac837
---- /dev/null
-+++ b/drivers/media/i2c/smiapp/ccs-limits.c
-@@ -0,0 +1,239 @@
-+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
-+/* Copyright (C) 2019--2020 Intel Corporation */
-+
-+#include "ccs-limits.h"
-+#include "ccs-regs.h"
-+
-+const struct ccs_limit ccs_limits[] = {
-+ { CCS_R_FRAME_FORMAT_MODEL_TYPE, 1, 0, "frame_format_model_type" },
-+ { CCS_R_FRAME_FORMAT_MODEL_SUBTYPE, 1, 0, "frame_format_model_subtype" },
-+ { CCS_R_FRAME_FORMAT_DESCRIPTOR(0), 30, 0, "frame_format_descriptor" },
-+ { CCS_R_FRAME_FORMAT_DESCRIPTOR_4(0), 32, 0, "frame_format_descriptor_4" },
-+ { CCS_R_ANALOG_GAIN_CAPABILITY, 2, 0, "analog_gain_capability" },
-+ { CCS_R_ANALOG_GAIN_CODE_MIN, 2, 0, "analog_gain_code_min" },
-+ { CCS_R_ANALOG_GAIN_CODE_MAX, 2, 0, "analog_gain_code_max" },
-+ { CCS_R_ANALOG_GAIN_CODE_STEP, 2, 0, "analog_gain_code_step" },
-+ { CCS_R_ANALOG_GAIN_TYPE, 2, 0, "analog_gain_type" },
-+ { CCS_R_ANALOG_GAIN_M0, 2, 0, "analog_gain_m0" },
-+ { CCS_R_ANALOG_GAIN_C0, 2, 0, "analog_gain_c0" },
-+ { CCS_R_ANALOG_GAIN_M1, 2, 0, "analog_gain_m1" },
-+ { CCS_R_ANALOG_GAIN_C1, 2, 0, "analog_gain_c1" },
-+ { CCS_R_ANALOG_LINEAR_GAIN_MIN, 2, 0, "analog_linear_gain_min" },
-+ { CCS_R_ANALOG_LINEAR_GAIN_MAX, 2, 0, "analog_linear_gain_max" },
-+ { CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE, 2, 0, "analog_linear_gain_step_size" },
-+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN, 2, 0, "analog_exponential_gain_min" },
-+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX, 2, 0, "analog_exponential_gain_max" },
-+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE, 2, 0, "analog_exponential_gain_step_size" },
-+ { CCS_R_DATA_FORMAT_MODEL_TYPE, 1, 0, "data_format_model_type" },
-+ { CCS_R_DATA_FORMAT_MODEL_SUBTYPE, 1, 0, "data_format_model_subtype" },
-+ { CCS_R_DATA_FORMAT_DESCRIPTOR(0), 32, 0, "data_format_descriptor" },
-+ { CCS_R_INTEGRATION_TIME_CAPABILITY, 2, 0, "integration_time_capability" },
-+ { CCS_R_COARSE_INTEGRATION_TIME_MIN, 2, 0, "coarse_integration_time_min" },
-+ { CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "coarse_integration_time_max_margin" },
-+ { CCS_R_FINE_INTEGRATION_TIME_MIN, 2, 0, "fine_integration_time_min" },
-+ { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "fine_integration_time_max_margin" },
-+ { CCS_R_DIGITAL_GAIN_CAPABILITY, 1, 0, "digital_gain_capability" },
-+ { CCS_R_DIGITAL_GAIN_MIN, 2, 0, "digital_gain_min" },
-+ { CCS_R_DIGITAL_GAIN_MAX, 2, 0, "digital_gain_max" },
-+ { CCS_R_DIGITAL_GAIN_STEP_SIZE, 2, 0, "digital_gain_step_size" },
-+ { CCS_R_PEDESTAL_CAPABILITY, 1, 0, "Pedestal_capability" },
-+ { CCS_R_ADC_CAPABILITY, 1, 0, "ADC_capability" },
-+ { CCS_R_ADC_BIT_DEPTH_CAPABILITY, 4, 0, "ADC_bit_depth_capability" },
-+ { CCS_R_MIN_EXT_CLK_FREQ_MHZ, 4, 0, "min_ext_clk_freq_mhz" },
-+ { CCS_R_MAX_EXT_CLK_FREQ_MHZ, 4, 0, "max_ext_clk_freq_mhz" },
-+ { CCS_R_MIN_PRE_PLL_CLK_DIV, 2, 0, "min_pre_pll_clk_div" },
-+ { CCS_R_MAX_PRE_PLL_CLK_DIV, 2, 0, "max_pre_pll_clk_div" },
-+ { CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_pll_ip_clk_freq_mhz" },
-+ { CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_pll_ip_clk_freq_mhz" },
-+ { CCS_R_MIN_PLL_MULTIPLIER, 2, 0, "min_pll_multiplier" },
-+ { CCS_R_MAX_PLL_MULTIPLIER, 2, 0, "max_pll_multiplier" },
-+ { CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_pll_op_clk_freq_mhz" },
-+ { CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_pll_op_clk_freq_mhz" },
-+ { CCS_R_MIN_VT_SYS_CLK_DIV, 2, 0, "min_vt_sys_clk_div" },
-+ { CCS_R_MAX_VT_SYS_CLK_DIV, 2, 0, "max_vt_sys_clk_div" },
-+ { CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ, 4, 0, "min_vt_sys_clk_freq_mhz" },
-+ { CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ, 4, 0, "max_vt_sys_clk_freq_mhz" },
-+ { CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ, 4, 0, "min_vt_pix_clk_freq_mhz" },
-+ { CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ, 4, 0, "max_vt_pix_clk_freq_mhz" },
-+ { CCS_R_MIN_VT_PIX_CLK_DIV, 2, 0, "min_vt_pix_clk_div" },
-+ { CCS_R_MAX_VT_PIX_CLK_DIV, 2, 0, "max_vt_pix_clk_div" },
-+ { CCS_R_CLOCK_CALCULATION, 1, 0, "clock_calculation" },
-+ { CCS_R_NUM_OF_VT_LANES, 1, 0, "num_of_vt_lanes" },
-+ { CCS_R_NUM_OF_OP_LANES, 1, 0, "num_of_op_lanes" },
-+ { CCS_R_OP_BITS_PER_LANE, 1, 0, "op_bits_per_lane" },
-+ { CCS_R_MIN_FRAME_LENGTH_LINES, 2, 0, "min_frame_length_lines" },
-+ { CCS_R_MAX_FRAME_LENGTH_LINES, 2, 0, "max_frame_length_lines" },
-+ { CCS_R_MIN_LINE_LENGTH_PCK, 2, 0, "min_line_length_pck" },
-+ { CCS_R_MAX_LINE_LENGTH_PCK, 2, 0, "max_line_length_pck" },
-+ { CCS_R_MIN_LINE_BLANKING_PCK, 2, 0, "min_line_blanking_pck" },
-+ { CCS_R_MIN_FRAME_BLANKING_LINES, 2, 0, "min_frame_blanking_lines" },
-+ { CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE, 1, 0, "min_line_length_pck_step_size" },
-+ { CCS_R_TIMING_MODE_CAPABILITY, 1, 0, "timing_mode_capability" },
-+ { CCS_R_FRAME_MARGIN_MAX_VALUE, 2, 0, "frame_margin_max_value" },
-+ { CCS_R_FRAME_MARGIN_MIN_VALUE, 1, 0, "frame_margin_min_value" },
-+ { CCS_R_GAIN_DELAY_TYPE, 1, 0, "gain_delay_type" },
-+ { CCS_R_MIN_OP_SYS_CLK_DIV, 2, 0, "min_op_sys_clk_div" },
-+ { CCS_R_MAX_OP_SYS_CLK_DIV, 2, 0, "max_op_sys_clk_div" },
-+ { CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ, 4, 0, "min_op_sys_clk_freq_mhz" },
-+ { CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ, 4, 0, "max_op_sys_clk_freq_mhz" },
-+ { CCS_R_MIN_OP_PIX_CLK_DIV, 2, 0, "min_op_pix_clk_div" },
-+ { CCS_R_MAX_OP_PIX_CLK_DIV, 2, 0, "max_op_pix_clk_div" },
-+ { CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ, 4, 0, "min_op_pix_clk_freq_mhz" },
-+ { CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ, 4, 0, "max_op_pix_clk_freq_mhz" },
-+ { CCS_R_X_ADDR_MIN, 2, 0, "x_addr_min" },
-+ { CCS_R_Y_ADDR_MIN, 2, 0, "y_addr_min" },
-+ { CCS_R_X_ADDR_MAX, 2, 0, "x_addr_max" },
-+ { CCS_R_Y_ADDR_MAX, 2, 0, "y_addr_max" },
-+ { CCS_R_MIN_X_OUTPUT_SIZE, 2, 0, "min_x_output_size" },
-+ { CCS_R_MIN_Y_OUTPUT_SIZE, 2, 0, "min_y_output_size" },
-+ { CCS_R_MAX_X_OUTPUT_SIZE, 2, 0, "max_x_output_size" },
-+ { CCS_R_MAX_Y_OUTPUT_SIZE, 2, 0, "max_y_output_size" },
-+ { CCS_R_X_ADDR_START_DIV_CONSTANT, 1, 0, "x_addr_start_div_constant" },
-+ { CCS_R_Y_ADDR_START_DIV_CONSTANT, 1, 0, "y_addr_start_div_constant" },
-+ { CCS_R_X_ADDR_END_DIV_CONSTANT, 1, 0, "x_addr_end_div_constant" },
-+ { CCS_R_Y_ADDR_END_DIV_CONSTANT, 1, 0, "y_addr_end_div_constant" },
-+ { CCS_R_X_SIZE_DIV, 1, 0, "x_size_div" },
-+ { CCS_R_Y_SIZE_DIV, 1, 0, "y_size_div" },
-+ { CCS_R_X_OUTPUT_DIV, 1, 0, "x_output_div" },
-+ { CCS_R_Y_OUTPUT_DIV, 1, 0, "y_output_div" },
-+ { CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT, 1, 0, "non_flexible_resolution_support" },
-+ { CCS_R_MIN_OP_PRE_PLL_CLK_DIV, 2, 0, "min_op_pre_pll_clk_div" },
-+ { CCS_R_MAX_OP_PRE_PLL_CLK_DIV, 2, 0, "max_op_pre_pll_clk_div" },
-+ { CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_ip_clk_freq_mhz" },
-+ { CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_ip_clk_freq_mhz" },
-+ { CCS_R_MIN_OP_PLL_MULTIPLIER, 2, 0, "min_op_pll_multiplier" },
-+ { CCS_R_MAX_OP_PLL_MULTIPLIER, 2, 0, "max_op_pll_multiplier" },
-+ { CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_op_clk_freq_mhz" },
-+ { CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_op_clk_freq_mhz" },
-+ { CCS_R_CLOCK_TREE_PLL_CAPABILITY, 1, 0, "clock_tree_pll_capability" },
-+ { CCS_R_CLOCK_CAPA_TYPE_CAPABILITY, 1, 0, "clock_capa_type_capability" },
-+ { CCS_R_MIN_EVEN_INC, 2, 0, "min_even_inc" },
-+ { CCS_R_MIN_ODD_INC, 2, 0, "min_odd_inc" },
-+ { CCS_R_MAX_EVEN_INC, 2, 0, "max_even_inc" },
-+ { CCS_R_MAX_ODD_INC, 2, 0, "max_odd_inc" },
-+ { CCS_R_AUX_SUBSAMP_CAPABILITY, 1, 0, "aux_subsamp_capability" },
-+ { CCS_R_AUX_SUBSAMP_MONO_CAPABILITY, 1, 0, "aux_subsamp_mono_capability" },
-+ { CCS_R_MONOCHROME_CAPABILITY, 1, 0, "monochrome_capability" },
-+ { CCS_R_PIXEL_READOUT_CAPABILITY, 1, 0, "pixel_readout_capability" },
-+ { CCS_R_MIN_EVEN_INC_MONO, 2, 0, "min_even_inc_mono" },
-+ { CCS_R_MAX_EVEN_INC_MONO, 2, 0, "max_even_inc_mono" },
-+ { CCS_R_MIN_ODD_INC_MONO, 2, 0, "min_odd_inc_mono" },
-+ { CCS_R_MAX_ODD_INC_MONO, 2, 0, "max_odd_inc_mono" },
-+ { CCS_R_MIN_EVEN_INC_BC2, 2, 0, "min_even_inc_bc2" },
-+ { CCS_R_MAX_EVEN_INC_BC2, 2, 0, "max_even_inc_bc2" },
-+ { CCS_R_MIN_ODD_INC_BC2, 2, 0, "min_odd_inc_bc2" },
-+ { CCS_R_MAX_ODD_INC_BC2, 2, 0, "max_odd_inc_bc2" },
-+ { CCS_R_MIN_EVEN_INC_MONO_BC2, 2, 0, "min_even_inc_mono_bc2" },
-+ { CCS_R_MAX_EVEN_INC_MONO_BC2, 2, 0, "max_even_inc_mono_bc2" },
-+ { CCS_R_MIN_ODD_INC_MONO_BC2, 2, 0, "min_odd_inc_mono_bc2" },
-+ { CCS_R_MAX_ODD_INC_MONO_BC2, 2, 0, "max_odd_inc_mono_bc2" },
-+ { CCS_R_SCALING_CAPABILITY, 2, 0, "scaling_capability" },
-+ { CCS_R_SCALER_M_MIN, 2, 0, "scaler_m_min" },
-+ { CCS_R_SCALER_M_MAX, 2, 0, "scaler_m_max" },
-+ { CCS_R_SCALER_N_MIN, 2, 0, "scaler_n_min" },
-+ { CCS_R_SCALER_N_MAX, 2, 0, "scaler_n_max" },
-+ { CCS_R_DIGITAL_CROP_CAPABILITY, 1, 0, "digital_crop_capability" },
-+ { CCS_R_HDR_CAPABILITY_1, 1, 0, "hdr_capability_1" },
-+ { CCS_R_MIN_HDR_BIT_DEPTH, 1, 0, "min_hdr_bit_depth" },
-+ { CCS_R_HDR_RESOLUTION_SUB_TYPES, 1, 0, "hdr_resolution_sub_types" },
-+ { CCS_R_HDR_RESOLUTION_SUB_TYPE(0), 2, 0, "hdr_resolution_sub_type" },
-+ { CCS_R_HDR_CAPABILITY_2, 1, 0, "hdr_capability_2" },
-+ { CCS_R_MAX_HDR_BIT_DEPTH, 1, 0, "max_hdr_bit_depth" },
-+ { CCS_R_USL_SUPPORT_CAPABILITY, 1, 0, "usl_support_capability" },
-+ { CCS_R_USL_CLOCK_MODE_D_CAPABILITY, 1, 0, "usl_clock_mode_d_capability" },
-+ { CCS_R_MIN_OP_SYS_CLK_DIV_REV, 1, 0, "min_op_sys_clk_div_rev" },
-+ { CCS_R_MAX_OP_SYS_CLK_DIV_REV, 1, 0, "max_op_sys_clk_div_rev" },
-+ { CCS_R_MIN_OP_PIX_CLK_DIV_REV, 1, 0, "min_op_pix_clk_div_rev" },
-+ { CCS_R_MAX_OP_PIX_CLK_DIV_REV, 1, 0, "max_op_pix_clk_div_rev" },
-+ { CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "min_op_sys_clk_freq_rev_mhz" },
-+ { CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "max_op_sys_clk_freq_rev_mhz" },
-+ { CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "min_op_pix_clk_freq_rev_mhz" },
-+ { CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "max_op_pix_clk_freq_rev_mhz" },
-+ { CCS_R_MAX_BITRATE_REV_D_MODE_MBPS, 4, 0, "max_bitrate_rev_d_mode_mbps" },
-+ { CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS, 4, 0, "max_symrate_rev_c_mode_msps" },
-+ { CCS_R_COMPRESSION_CAPABILITY, 1, 0, "compression_capability" },
-+ { CCS_R_TEST_MODE_CAPABILITY, 2, 0, "test_mode_capability" },
-+ { CCS_R_PN9_DATA_FORMAT1, 1, 0, "pn9_data_format1" },
-+ { CCS_R_PN9_DATA_FORMAT2, 1, 0, "pn9_data_format2" },
-+ { CCS_R_PN9_DATA_FORMAT3, 1, 0, "pn9_data_format3" },
-+ { CCS_R_PN9_DATA_FORMAT4, 1, 0, "pn9_data_format4" },
-+ { CCS_R_PN9_MISC_CAPABILITY, 1, 0, "pn9_misc_capability" },
-+ { CCS_R_TEST_PATTERN_CAPABILITY, 1, 0, "test_pattern_capability" },
-+ { CCS_R_PATTERN_SIZE_DIV_M1, 1, 0, "pattern_size_div_m1" },
-+ { CCS_R_FIFO_SUPPORT_CAPABILITY, 1, 0, "fifo_support_capability" },
-+ { CCS_R_PHY_CTRL_CAPABILITY, 1, 0, "phy_ctrl_capability" },
-+ { CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_dphy_lane_mode_capability" },
-+ { CCS_R_CSI_SIGNALING_MODE_CAPABILITY, 1, 0, "csi_signaling_mode_capability" },
-+ { CCS_R_FAST_STANDBY_CAPABILITY, 1, 0, "fast_standby_capability" },
-+ { CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY, 1, 0, "csi_address_control_capability" },
-+ { CCS_R_DATA_TYPE_CAPABILITY, 1, 0, "data_type_capability" },
-+ { CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_cphy_lane_mode_capability" },
-+ { CCS_R_EMB_DATA_CAPABILITY, 1, 0, "emb_data_capability" },
-+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_d_mode_mbps 0" },
-+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_d_mode_mbps 4" },
-+ { CCS_R_TEMP_SENSOR_CAPABILITY, 1, 0, "temp_sensor_capability" },
-+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_c_mode_mbps 0" },
-+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_c_mode_mbps 4" },
-+ { CCS_R_DPHY_EQUALIZATION_CAPABILITY, 1, 0, "dphy_equalization_capability" },
-+ { CCS_R_CPHY_EQUALIZATION_CAPABILITY, 1, 0, "cphy_equalization_capability" },
-+ { CCS_R_DPHY_PREAMBLE_CAPABILITY, 1, 0, "dphy_preamble_capability" },
-+ { CCS_R_DPHY_SSC_CAPABILITY, 1, 0, "dphy_ssc_capability" },
-+ { CCS_R_CPHY_CALIBRATION_CAPABILITY, 1, 0, "cphy_calibration_capability" },
-+ { CCS_R_DPHY_CALIBRATION_CAPABILITY, 1, 0, "dphy_calibration_capability" },
-+ { CCS_R_PHY_CTRL_CAPABILITY_2, 1, 0, "phy_ctrl_capability_2" },
-+ { CCS_R_LRTE_CPHY_CAPABILITY, 1, 0, "lrte_cphy_capability" },
-+ { CCS_R_LRTE_DPHY_CAPABILITY, 1, 0, "lrte_dphy_capability" },
-+ { CCS_R_ALPS_CAPABILITY_DPHY, 1, 0, "alps_capability_dphy" },
-+ { CCS_R_ALPS_CAPABILITY_CPHY, 1, 0, "alps_capability_cphy" },
-+ { CCS_R_SCRAMBLING_CAPABILITY, 1, 0, "scrambling_capability" },
-+ { CCS_R_DPHY_MANUAL_CONSTANT, 1, 0, "dphy_manual_constant" },
-+ { CCS_R_CPHY_MANUAL_CONSTANT, 1, 0, "cphy_manual_constant" },
-+ { CCS_R_CSI2_INTERFACE_CAPABILITY_MISC, 1, 0, "CSI2_interface_capability_misc" },
-+ { CCS_R_PHY_CTRL_CAPABILITY_3, 1, 0, "PHY_ctrl_capability_3" },
-+ { CCS_R_DPHY_SF, 1, 0, "dphy_sf" },
-+ { CCS_R_CPHY_SF, 1, 0, "cphy_sf" },
-+ { CCS_R_DPHY_LIMITS_1, 1, 0, "dphy_limits_1" },
-+ { CCS_R_DPHY_LIMITS_2, 1, 0, "dphy_limits_2" },
-+ { CCS_R_DPHY_LIMITS_3, 1, 0, "dphy_limits_3" },
-+ { CCS_R_DPHY_LIMITS_4, 1, 0, "dphy_limits_4" },
-+ { CCS_R_DPHY_LIMITS_5, 1, 0, "dphy_limits_5" },
-+ { CCS_R_DPHY_LIMITS_6, 1, 0, "dphy_limits_6" },
-+ { CCS_R_CPHY_LIMITS_1, 1, 0, "cphy_limits_1" },
-+ { CCS_R_CPHY_LIMITS_2, 1, 0, "cphy_limits_2" },
-+ { CCS_R_CPHY_LIMITS_3, 1, 0, "cphy_limits_3" },
-+ { CCS_R_MIN_FRAME_LENGTH_LINES_BIN, 2, 0, "min_frame_length_lines_bin" },
-+ { CCS_R_MAX_FRAME_LENGTH_LINES_BIN, 2, 0, "max_frame_length_lines_bin" },
-+ { CCS_R_MIN_LINE_LENGTH_PCK_BIN, 2, 0, "min_line_length_pck_bin" },
-+ { CCS_R_MAX_LINE_LENGTH_PCK_BIN, 2, 0, "max_line_length_pck_bin" },
-+ { CCS_R_MIN_LINE_BLANKING_PCK_BIN, 2, 0, "min_line_blanking_pck_bin" },
-+ { CCS_R_FINE_INTEGRATION_TIME_MIN_BIN, 2, 0, "fine_integration_time_min_bin" },
-+ { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, 2, 0, "fine_integration_time_max_margin_bin" },
-+ { CCS_R_BINNING_CAPABILITY, 1, 0, "binning_capability" },
-+ { CCS_R_BINNING_WEIGHTING_CAPABILITY, 1, 0, "binning_weighting_capability" },
-+ { CCS_R_BINNING_SUB_TYPES, 1, 0, "binning_sub_types" },
-+ { CCS_R_BINNING_SUB_TYPE(0), 64, 0, "binning_sub_type" },
-+ { CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY, 1, 0, "binning_weighting_mono_capability" },
-+ { CCS_R_BINNING_SUB_TYPES_MONO, 1, 0, "binning_sub_types_mono" },
-+ { CCS_R_BINNING_SUB_TYPE_MONO(0), 64, 0, "binning_sub_type_mono" },
-+ { CCS_R_DATA_TRANSFER_IF_CAPABILITY, 1, 0, "data_transfer_if_capability" },
-+ { CCS_R_SHADING_CORRECTION_CAPABILITY, 1, 0, "shading_correction_capability" },
-+ { CCS_R_GREEN_IMBALANCE_CAPABILITY, 1, 0, "green_imbalance_capability" },
-+ { CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY, 1, 0, "module_specific_correction_capability" },
-+ { CCS_R_DEFECT_CORRECTION_CAPABILITY, 2, 0, "defect_correction_capability" },
-+ { CCS_R_DEFECT_CORRECTION_CAPABILITY_2, 2, 0, "defect_correction_capability_2" },
-+ { CCS_R_NF_CAPABILITY, 1, 0, "nf_capability" },
-+ { CCS_R_OB_READOUT_CAPABILITY, 1, 0, "ob_readout_capability" },
-+ { CCS_R_COLOR_FEEDBACK_CAPABILITY, 1, 0, "color_feedback_capability" },
-+ { CCS_R_CFA_PATTERN_CAPABILITY, 1, 0, "CFA_pattern_capability" },
-+ { CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY, 1, 0, "CFA_pattern_conversion_capability" },
-+ { CCS_R_FLASH_MODE_CAPABILITY, 1, 0, "flash_mode_capability" },
-+ { CCS_R_SA_STROBE_MODE_CAPABILITY, 1, 0, "sa_strobe_mode_capability" },
-+ { CCS_R_RESET_MAX_DELAY, 1, 0, "reset_max_delay" },
-+ { CCS_R_RESET_MIN_TIME, 1, 0, "reset_min_time" },
-+ { CCS_R_PDAF_CAPABILITY_1, 1, 0, "pdaf_capability_1" },
-+ { CCS_R_PDAF_CAPABILITY_2, 1, 0, "pdaf_capability_2" },
-+ { CCS_R_BRACKETING_LUT_CAPABILITY_1, 1, 0, "bracketing_lut_capability_1" },
-+ { CCS_R_BRACKETING_LUT_CAPABILITY_2, 1, 0, "bracketing_lut_capability_2" },
-+ { CCS_R_BRACKETING_LUT_SIZE, 1, 0, "bracketing_lut_size" },
-+ { 0 } /* Guardian */
-+};
-diff --git a/drivers/media/i2c/smiapp/ccs-limits.h b/drivers/media/i2c/smiapp/ccs-limits.h
-new file mode 100644
-index 0000000000000..1efa43c23a2eb
---- /dev/null
-+++ b/drivers/media/i2c/smiapp/ccs-limits.h
-@@ -0,0 +1,259 @@
-+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
-+/* Copyright (C) 2019--2020 Intel Corporation */
-+
-+#ifndef __CCS_LIMITS_H__
-+#define __CCS_LIMITS_H__
-+
-+#include <linux/bits.h>
-+#include <linux/types.h>
-+
-+struct ccs_limit {
-+ u32 reg;
-+ u16 size;
-+ u16 flags;
-+ const char *name;
-+};
-+
-+#define CCS_L_FL_SAME_REG BIT(0)
-+
-+extern const struct ccs_limit ccs_limits[];
-+
-+#define CCS_L_FRAME_FORMAT_MODEL_TYPE 0
-+#define CCS_L_FRAME_FORMAT_MODEL_SUBTYPE 1
-+#define CCS_L_FRAME_FORMAT_DESCRIPTOR 2
-+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2)
-+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4 3
-+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4_OFFSET(n) ((n) * 4)
-+#define CCS_L_ANALOG_GAIN_CAPABILITY 4
-+#define CCS_L_ANALOG_GAIN_CODE_MIN 5
-+#define CCS_L_ANALOG_GAIN_CODE_MAX 6
-+#define CCS_L_ANALOG_GAIN_CODE_STEP 7
-+#define CCS_L_ANALOG_GAIN_TYPE 8
-+#define CCS_L_ANALOG_GAIN_M0 9
-+#define CCS_L_ANALOG_GAIN_C0 10
-+#define CCS_L_ANALOG_GAIN_M1 11
-+#define CCS_L_ANALOG_GAIN_C1 12
-+#define CCS_L_ANALOG_LINEAR_GAIN_MIN 13
-+#define CCS_L_ANALOG_LINEAR_GAIN_MAX 14
-+#define CCS_L_ANALOG_LINEAR_GAIN_STEP_SIZE 15
-+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MIN 16
-+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MAX 17
-+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE 18
-+#define CCS_L_DATA_FORMAT_MODEL_TYPE 19
-+#define CCS_L_DATA_FORMAT_MODEL_SUBTYPE 20
-+#define CCS_L_DATA_FORMAT_DESCRIPTOR 21
-+#define CCS_L_DATA_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2)
-+#define CCS_L_INTEGRATION_TIME_CAPABILITY 22
-+#define CCS_L_COARSE_INTEGRATION_TIME_MIN 23
-+#define CCS_L_COARSE_INTEGRATION_TIME_MAX_MARGIN 24
-+#define CCS_L_FINE_INTEGRATION_TIME_MIN 25
-+#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN 26
-+#define CCS_L_DIGITAL_GAIN_CAPABILITY 27
-+#define CCS_L_DIGITAL_GAIN_MIN 28
-+#define CCS_L_DIGITAL_GAIN_MAX 29
-+#define CCS_L_DIGITAL_GAIN_STEP_SIZE 30
-+#define CCS_L_PEDESTAL_CAPABILITY 31
-+#define CCS_L_ADC_CAPABILITY 32
-+#define CCS_L_ADC_BIT_DEPTH_CAPABILITY 33
-+#define CCS_L_MIN_EXT_CLK_FREQ_MHZ 34
-+#define CCS_L_MAX_EXT_CLK_FREQ_MHZ 35
-+#define CCS_L_MIN_PRE_PLL_CLK_DIV 36
-+#define CCS_L_MAX_PRE_PLL_CLK_DIV 37
-+#define CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ 38
-+#define CCS_L_MAX_PLL_IP_CLK_FREQ_MHZ 39
-+#define CCS_L_MIN_PLL_MULTIPLIER 40
-+#define CCS_L_MAX_PLL_MULTIPLIER 41
-+#define CCS_L_MIN_PLL_OP_CLK_FREQ_MHZ 42
-+#define CCS_L_MAX_PLL_OP_CLK_FREQ_MHZ 43
-+#define CCS_L_MIN_VT_SYS_CLK_DIV 44
-+#define CCS_L_MAX_VT_SYS_CLK_DIV 45
-+#define CCS_L_MIN_VT_SYS_CLK_FREQ_MHZ 46
-+#define CCS_L_MAX_VT_SYS_CLK_FREQ_MHZ 47
-+#define CCS_L_MIN_VT_PIX_CLK_FREQ_MHZ 48
-+#define CCS_L_MAX_VT_PIX_CLK_FREQ_MHZ 49
-+#define CCS_L_MIN_VT_PIX_CLK_DIV 50
-+#define CCS_L_MAX_VT_PIX_CLK_DIV 51
-+#define CCS_L_CLOCK_CALCULATION 52
-+#define CCS_L_NUM_OF_VT_LANES 53
-+#define CCS_L_NUM_OF_OP_LANES 54
-+#define CCS_L_OP_BITS_PER_LANE 55
-+#define CCS_L_MIN_FRAME_LENGTH_LINES 56
-+#define CCS_L_MAX_FRAME_LENGTH_LINES 57
-+#define CCS_L_MIN_LINE_LENGTH_PCK 58
-+#define CCS_L_MAX_LINE_LENGTH_PCK 59
-+#define CCS_L_MIN_LINE_BLANKING_PCK 60
-+#define CCS_L_MIN_FRAME_BLANKING_LINES 61
-+#define CCS_L_MIN_LINE_LENGTH_PCK_STEP_SIZE 62
-+#define CCS_L_TIMING_MODE_CAPABILITY 63
-+#define CCS_L_FRAME_MARGIN_MAX_VALUE 64
-+#define CCS_L_FRAME_MARGIN_MIN_VALUE 65
-+#define CCS_L_GAIN_DELAY_TYPE 66
-+#define CCS_L_MIN_OP_SYS_CLK_DIV 67
-+#define CCS_L_MAX_OP_SYS_CLK_DIV 68
-+#define CCS_L_MIN_OP_SYS_CLK_FREQ_MHZ 69
-+#define CCS_L_MAX_OP_SYS_CLK_FREQ_MHZ 70
-+#define CCS_L_MIN_OP_PIX_CLK_DIV 71
-+#define CCS_L_MAX_OP_PIX_CLK_DIV 72
-+#define CCS_L_MIN_OP_PIX_CLK_FREQ_MHZ 73
-+#define CCS_L_MAX_OP_PIX_CLK_FREQ_MHZ 74
-+#define CCS_L_X_ADDR_MIN 75
-+#define CCS_L_Y_ADDR_MIN 76
-+#define CCS_L_X_ADDR_MAX 77
-+#define CCS_L_Y_ADDR_MAX 78
-+#define CCS_L_MIN_X_OUTPUT_SIZE 79
-+#define CCS_L_MIN_Y_OUTPUT_SIZE 80
-+#define CCS_L_MAX_X_OUTPUT_SIZE 81
-+#define CCS_L_MAX_Y_OUTPUT_SIZE 82
-+#define CCS_L_X_ADDR_START_DIV_CONSTANT 83
-+#define CCS_L_Y_ADDR_START_DIV_CONSTANT 84
-+#define CCS_L_X_ADDR_END_DIV_CONSTANT 85
-+#define CCS_L_Y_ADDR_END_DIV_CONSTANT 86
-+#define CCS_L_X_SIZE_DIV 87
-+#define CCS_L_Y_SIZE_DIV 88
-+#define CCS_L_X_OUTPUT_DIV 89
-+#define CCS_L_Y_OUTPUT_DIV 90
-+#define CCS_L_NON_FLEXIBLE_RESOLUTION_SUPPORT 91
-+#define CCS_L_MIN_OP_PRE_PLL_CLK_DIV 92
-+#define CCS_L_MAX_OP_PRE_PLL_CLK_DIV 93
-+#define CCS_L_MIN_OP_PLL_IP_CLK_FREQ_MHZ 94
-+#define CCS_L_MAX_OP_PLL_IP_CLK_FREQ_MHZ 95
-+#define CCS_L_MIN_OP_PLL_MULTIPLIER 96
-+#define CCS_L_MAX_OP_PLL_MULTIPLIER 97
-+#define CCS_L_MIN_OP_PLL_OP_CLK_FREQ_MHZ 98
-+#define CCS_L_MAX_OP_PLL_OP_CLK_FREQ_MHZ 99
-+#define CCS_L_CLOCK_TREE_PLL_CAPABILITY 100
-+#define CCS_L_CLOCK_CAPA_TYPE_CAPABILITY 101
-+#define CCS_L_MIN_EVEN_INC 102
-+#define CCS_L_MIN_ODD_INC 103
-+#define CCS_L_MAX_EVEN_INC 104
-+#define CCS_L_MAX_ODD_INC 105
-+#define CCS_L_AUX_SUBSAMP_CAPABILITY 106
-+#define CCS_L_AUX_SUBSAMP_MONO_CAPABILITY 107
-+#define CCS_L_MONOCHROME_CAPABILITY 108
-+#define CCS_L_PIXEL_READOUT_CAPABILITY 109
-+#define CCS_L_MIN_EVEN_INC_MONO 110
-+#define CCS_L_MAX_EVEN_INC_MONO 111
-+#define CCS_L_MIN_ODD_INC_MONO 112
-+#define CCS_L_MAX_ODD_INC_MONO 113
-+#define CCS_L_MIN_EVEN_INC_BC2 114
-+#define CCS_L_MAX_EVEN_INC_BC2 115
-+#define CCS_L_MIN_ODD_INC_BC2 116
-+#define CCS_L_MAX_ODD_INC_BC2 117
-+#define CCS_L_MIN_EVEN_INC_MONO_BC2 118
-+#define CCS_L_MAX_EVEN_INC_MONO_BC2 119
-+#define CCS_L_MIN_ODD_INC_MONO_BC2 120
-+#define CCS_L_MAX_ODD_INC_MONO_BC2 121
-+#define CCS_L_SCALING_CAPABILITY 122
-+#define CCS_L_SCALER_M_MIN 123
-+#define CCS_L_SCALER_M_MAX 124
-+#define CCS_L_SCALER_N_MIN 125
-+#define CCS_L_SCALER_N_MAX 126
-+#define CCS_L_DIGITAL_CROP_CAPABILITY 127
-+#define CCS_L_HDR_CAPABILITY_1 128
-+#define CCS_L_MIN_HDR_BIT_DEPTH 129
-+#define CCS_L_HDR_RESOLUTION_SUB_TYPES 130
-+#define CCS_L_HDR_RESOLUTION_SUB_TYPE 131
-+#define CCS_L_HDR_RESOLUTION_SUB_TYPE_OFFSET(n) (n)
-+#define CCS_L_HDR_CAPABILITY_2 132
-+#define CCS_L_MAX_HDR_BIT_DEPTH 133
-+#define CCS_L_USL_SUPPORT_CAPABILITY 134
-+#define CCS_L_USL_CLOCK_MODE_D_CAPABILITY 135
-+#define CCS_L_MIN_OP_SYS_CLK_DIV_REV 136
-+#define CCS_L_MAX_OP_SYS_CLK_DIV_REV 137
-+#define CCS_L_MIN_OP_PIX_CLK_DIV_REV 138
-+#define CCS_L_MAX_OP_PIX_CLK_DIV_REV 139
-+#define CCS_L_MIN_OP_SYS_CLK_FREQ_REV_MHZ 140
-+#define CCS_L_MAX_OP_SYS_CLK_FREQ_REV_MHZ 141
-+#define CCS_L_MIN_OP_PIX_CLK_FREQ_REV_MHZ 142
-+#define CCS_L_MAX_OP_PIX_CLK_FREQ_REV_MHZ 143
-+#define CCS_L_MAX_BITRATE_REV_D_MODE_MBPS 144
-+#define CCS_L_MAX_SYMRATE_REV_C_MODE_MSPS 145
-+#define CCS_L_COMPRESSION_CAPABILITY 146
-+#define CCS_L_TEST_MODE_CAPABILITY 147
-+#define CCS_L_PN9_DATA_FORMAT1 148
-+#define CCS_L_PN9_DATA_FORMAT2 149
-+#define CCS_L_PN9_DATA_FORMAT3 150
-+#define CCS_L_PN9_DATA_FORMAT4 151
-+#define CCS_L_PN9_MISC_CAPABILITY 152
-+#define CCS_L_TEST_PATTERN_CAPABILITY 153
-+#define CCS_L_PATTERN_SIZE_DIV_M1 154
-+#define CCS_L_FIFO_SUPPORT_CAPABILITY 155
-+#define CCS_L_PHY_CTRL_CAPABILITY 156
-+#define CCS_L_CSI_DPHY_LANE_MODE_CAPABILITY 157
-+#define CCS_L_CSI_SIGNALING_MODE_CAPABILITY 158
-+#define CCS_L_FAST_STANDBY_CAPABILITY 159
-+#define CCS_L_CSI_ADDRESS_CONTROL_CAPABILITY 160
-+#define CCS_L_DATA_TYPE_CAPABILITY 161
-+#define CCS_L_CSI_CPHY_LANE_MODE_CAPABILITY 162
-+#define CCS_L_EMB_DATA_CAPABILITY 163
-+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS 164
-+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_OFFSET(n) ((n) * 4)
-+#define CCS_L_TEMP_SENSOR_CAPABILITY 165
-+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS 166
-+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_OFFSET(n) ((n) * 4)
-+#define CCS_L_DPHY_EQUALIZATION_CAPABILITY 167
-+#define CCS_L_CPHY_EQUALIZATION_CAPABILITY 168
-+#define CCS_L_DPHY_PREAMBLE_CAPABILITY 169
-+#define CCS_L_DPHY_SSC_CAPABILITY 170
-+#define CCS_L_CPHY_CALIBRATION_CAPABILITY 171
-+#define CCS_L_DPHY_CALIBRATION_CAPABILITY 172
-+#define CCS_L_PHY_CTRL_CAPABILITY_2 173
-+#define CCS_L_LRTE_CPHY_CAPABILITY 174
-+#define CCS_L_LRTE_DPHY_CAPABILITY 175
-+#define CCS_L_ALPS_CAPABILITY_DPHY 176
-+#define CCS_L_ALPS_CAPABILITY_CPHY 177
-+#define CCS_L_SCRAMBLING_CAPABILITY 178
-+#define CCS_L_DPHY_MANUAL_CONSTANT 179
-+#define CCS_L_CPHY_MANUAL_CONSTANT 180
-+#define CCS_L_CSI2_INTERFACE_CAPABILITY_MISC 181
-+#define CCS_L_PHY_CTRL_CAPABILITY_3 182
-+#define CCS_L_DPHY_SF 183
-+#define CCS_L_CPHY_SF 184
-+#define CCS_L_DPHY_LIMITS_1 185
-+#define CCS_L_DPHY_LIMITS_2 186
-+#define CCS_L_DPHY_LIMITS_3 187
-+#define CCS_L_DPHY_LIMITS_4 188
-+#define CCS_L_DPHY_LIMITS_5 189
-+#define CCS_L_DPHY_LIMITS_6 190
-+#define CCS_L_CPHY_LIMITS_1 191
-+#define CCS_L_CPHY_LIMITS_2 192
-+#define CCS_L_CPHY_LIMITS_3 193
-+#define CCS_L_MIN_FRAME_LENGTH_LINES_BIN 194
-+#define CCS_L_MAX_FRAME_LENGTH_LINES_BIN 195
-+#define CCS_L_MIN_LINE_LENGTH_PCK_BIN 196
-+#define CCS_L_MAX_LINE_LENGTH_PCK_BIN 197
-+#define CCS_L_MIN_LINE_BLANKING_PCK_BIN 198
-+#define CCS_L_FINE_INTEGRATION_TIME_MIN_BIN 199
-+#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN 200
-+#define CCS_L_BINNING_CAPABILITY 201
-+#define CCS_L_BINNING_WEIGHTING_CAPABILITY 202
-+#define CCS_L_BINNING_SUB_TYPES 203
-+#define CCS_L_BINNING_SUB_TYPE 204
-+#define CCS_L_BINNING_SUB_TYPE_OFFSET(n) (n)
-+#define CCS_L_BINNING_WEIGHTING_MONO_CAPABILITY 205
-+#define CCS_L_BINNING_SUB_TYPES_MONO 206
-+#define CCS_L_BINNING_SUB_TYPE_MONO 207
-+#define CCS_L_BINNING_SUB_TYPE_MONO_OFFSET(n) (n)
-+#define CCS_L_DATA_TRANSFER_IF_CAPABILITY 208
-+#define CCS_L_SHADING_CORRECTION_CAPABILITY 209
-+#define CCS_L_GREEN_IMBALANCE_CAPABILITY 210
-+#define CCS_L_MODULE_SPECIFIC_CORRECTION_CAPABILITY 211
-+#define CCS_L_DEFECT_CORRECTION_CAPABILITY 212
-+#define CCS_L_DEFECT_CORRECTION_CAPABILITY_2 213
-+#define CCS_L_NF_CAPABILITY 214
-+#define CCS_L_OB_READOUT_CAPABILITY 215
-+#define CCS_L_COLOR_FEEDBACK_CAPABILITY 216
-+#define CCS_L_CFA_PATTERN_CAPABILITY 217
-+#define CCS_L_CFA_PATTERN_CONVERSION_CAPABILITY 218
-+#define CCS_L_FLASH_MODE_CAPABILITY 219
-+#define CCS_L_SA_STROBE_MODE_CAPABILITY 220
-+#define CCS_L_RESET_MAX_DELAY 221
-+#define CCS_L_RESET_MIN_TIME 222
-+#define CCS_L_PDAF_CAPABILITY_1 223
-+#define CCS_L_PDAF_CAPABILITY_2 224
-+#define CCS_L_BRACKETING_LUT_CAPABILITY_1 225
-+#define CCS_L_BRACKETING_LUT_CAPABILITY_2 226
-+#define CCS_L_BRACKETING_LUT_SIZE 227
-+#define CCS_L_LAST 228
-+
-+#endif /* __CCS_LIMITS_H__ */
-diff --git a/drivers/media/i2c/smiapp/ccs-regs.h b/drivers/media/i2c/smiapp/ccs-regs.h
-new file mode 100644
-index 0000000000000..4b3e5df2121f8
---- /dev/null
-+++ b/drivers/media/i2c/smiapp/ccs-regs.h
-@@ -0,0 +1,954 @@
-+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
-+/* Copyright (C) 2019--2020 Intel Corporation */
-+
-+#ifndef __CCS_REGS_H__
-+#define __CCS_REGS_H__
-+
-+#include <linux/bits.h>
-+
-+#define CCS_FL_BASE 16
-+#define CCS_FL_16BIT BIT(CCS_FL_BASE)
-+#define CCS_FL_32BIT BIT(CCS_FL_BASE + 1)
-+#define CCS_FL_FLOAT_IREAL BIT(CCS_FL_BASE + 2)
-+#define CCS_FL_IREAL BIT(CCS_FL_BASE + 3)
-+#define CCS_R_ADDR(r) ((r) & 0xffff)
-+
-+#define CCS_R_MODULE_MODEL_ID (0x0000 | CCS_FL_16BIT)
-+#define CCS_R_MODULE_REVISION_NUMBER_MAJOR 0x0002
-+#define CCS_R_FRAME_COUNT 0x0005
-+#define CCS_R_PIXEL_ORDER 0x0006
-+#define CCS_PIXEL_ORDER_GRBG 0U
-+#define CCS_PIXEL_ORDER_RGGB 1U
-+#define CCS_PIXEL_ORDER_BGGR 2U
-+#define CCS_PIXEL_ORDER_GBRG 3U
-+#define CCS_R_MIPI_CCS_VERSION 0x0007
-+#define CCS_MIPI_CCS_VERSION_V1_0 0x10
-+#define CCS_MIPI_CCS_VERSION_V1_1 0x11
-+#define CCS_MIPI_CCS_VERSION_MAJOR_SHIFT 4U
-+#define CCS_MIPI_CCS_VERSION_MAJOR_MASK 0xf0
-+#define CCS_MIPI_CCS_VERSION_MINOR_SHIFT 0U
-+#define CCS_MIPI_CCS_VERSION_MINOR_MASK 0xf
-+#define CCS_R_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
-+#define CCS_R_MODULE_MANUFACTURER_ID (0x000e | CCS_FL_16BIT)
-+#define CCS_R_MODULE_REVISION_NUMBER_MINOR 0x0010
-+#define CCS_R_MODULE_DATE_YEAR 0x0012
-+#define CCS_R_MODULE_DATE_MONTH 0x0013
-+#define CCS_R_MODULE_DATE_DAY 0x0014
-+#define CCS_R_MODULE_DATE_PHASE 0x0015
-+#define CCS_MODULE_DATE_PHASE_SHIFT 0U
-+#define CCS_MODULE_DATE_PHASE_MASK 0x7
-+#define CCS_MODULE_DATE_PHASE_TS 0U
-+#define CCS_MODULE_DATE_PHASE_ES 1U
-+#define CCS_MODULE_DATE_PHASE_CS 2U
-+#define CCS_MODULE_DATE_PHASE_MP 3U
-+#define CCS_R_SENSOR_MODEL_ID (0x0016 | CCS_FL_16BIT)
-+#define CCS_R_SENSOR_REVISION_NUMBER 0x0018
-+#define CCS_R_SENSOR_FIRMWARE_VERSION 0x001a
-+#define CCS_R_SERIAL_NUMBER (0x001c | CCS_FL_32BIT)
-+#define CCS_R_SENSOR_MANUFACTURER_ID (0x0020 | CCS_FL_16BIT)
-+#define CCS_R_SENSOR_REVISION_NUMBER_16 (0x0022 | CCS_FL_16BIT)
-+#define CCS_R_FRAME_FORMAT_MODEL_TYPE 0x0040
-+#define CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE 1U
-+#define CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE 2U
-+#define CCS_R_FRAME_FORMAT_MODEL_SUBTYPE 0x0041
-+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
-+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
-+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U
-+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
-+#define CCS_R_FRAME_FORMAT_DESCRIPTOR(n) ((0x0042 | CCS_FL_16BIT) + (n) * 2)
-+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MIN_N 0U
-+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MAX_N 14U
-+#define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n) ((0x0060 | CCS_FL_32BIT) + (n) * 4)
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_SHIFT 0U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK 0xfff
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT 12U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK 0xf000
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED 1U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL 2U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL 3U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL 4U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL 5U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_0 8U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_1 9U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_2 10U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_3 11U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_4 12U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_5 13U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_6 14U
-+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MIN_N 0U
-+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MAX_N 7U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_SHIFT 0U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK 0xffff
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT 28U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK 0xf0000000
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_EMBEDDED 1U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DUMMY_PIXEL 2U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_BLACK_PIXEL 3U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DARK_PIXEL 4U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_VISIBLE_PIXEL 5U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_0 8U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_1 9U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_2 10U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_3 11U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_4 12U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_5 13U
-+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_6 14U
-+#define CCS_R_ANALOG_GAIN_CAPABILITY (0x0080 | CCS_FL_16BIT)
-+#define CCS_ANALOG_GAIN_CAPABILITY_GLOBAL 0U
-+#define CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL 2U
-+#define CCS_R_ANALOG_GAIN_CODE_MIN (0x0084 | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_GAIN_CODE_MAX (0x0086 | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_GAIN_CODE_STEP (0x0088 | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_GAIN_TYPE (0x008a | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_GAIN_M0 (0x008c | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_GAIN_C0 (0x008e | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_GAIN_M1 (0x0090 | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_GAIN_C1 (0x0092 | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_LINEAR_GAIN_MIN (0x0094 | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_LINEAR_GAIN_MAX (0x0096 | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE (0x0098 | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN (0x009a | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX (0x009c | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE (0x009e | CCS_FL_16BIT)
-+#define CCS_R_DATA_FORMAT_MODEL_TYPE 0x00c0
-+#define CCS_DATA_FORMAT_MODEL_TYPE_NORMAL 1U
-+#define CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED 2U
-+#define CCS_R_DATA_FORMAT_MODEL_SUBTYPE 0x00c1
-+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
-+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
-+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U
-+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
-+#define CCS_R_DATA_FORMAT_DESCRIPTOR(n) ((0x00c2 | CCS_FL_16BIT) + (n) * 2)
-+#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MIN_N 0U
-+#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N 15U
-+#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_SHIFT 0U
-+#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK 0xff
-+#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT 8U
-+#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_MASK 0xff00
-+#define CCS_R_MODE_SELECT 0x0100
-+#define CCS_MODE_SELECT_SOFTWARE_STANDBY 0U
-+#define CCS_MODE_SELECT_STREAMING 1U
-+#define CCS_R_IMAGE_ORIENTATION 0x0101
-+#define CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR BIT(0)
-+#define CCS_IMAGE_ORIENTATION_VERTICAL_FLIP BIT(1)
-+#define CCS_R_SOFTWARE_RESET 0x0103
-+#define CCS_SOFTWARE_RESET_OFF 0U
-+#define CCS_SOFTWARE_RESET_ON 1U
-+#define CCS_R_GROUPED_PARAMETER_HOLD 0x0104
-+#define CCS_R_MASK_CORRUPTED_FRAMES 0x0105
-+#define CCS_MASK_CORRUPTED_FRAMES_ALLOW 0U
-+#define CCS_MASK_CORRUPTED_FRAMES_MASK 1U
-+#define CCS_R_FAST_STANDBY_CTRL 0x0106
-+#define CCS_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0U
-+#define CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION 1U
-+#define CCS_R_CCI_ADDRESS_CTRL 0x0107
-+#define CCS_R_2ND_CCI_IF_CTRL 0x0108
-+#define CCS_2ND_CCI_IF_CTRL_ENABLE BIT(0)
-+#define CCS_2ND_CCI_IF_CTRL_ACK BIT(1)
-+#define CCS_R_2ND_CCI_ADDRESS_CTRL 0x0109
-+#define CCS_R_CSI_CHANNEL_IDENTIFIER 0x0110
-+#define CCS_R_CSI_SIGNALING_MODE 0x0111
-+#define CCS_CSI_SIGNALING_MODE_CSI_2_DPHY 2U
-+#define CCS_CSI_SIGNALING_MODE_CSI_2_CPHY 3U
-+#define CCS_R_CSI_DATA_FORMAT (0x0112 | CCS_FL_16BIT)
-+#define CCS_R_CSI_LANE_MODE 0x0114
-+#define CCS_R_DPCM_FRAME_DT 0x011d
-+#define CCS_R_BOTTOM_EMBEDDED_DATA_DT 0x011e
-+#define CCS_R_BOTTOM_EMBEDDED_DATA_VC 0x011f
-+#define CCS_R_GAIN_MODE 0x0120
-+#define CCS_GAIN_MODE_GLOBAL 0U
-+#define CCS_GAIN_MODE_ALTERNATE 1U
-+#define CCS_R_ADC_BIT_DEPTH 0x0121
-+#define CCS_R_EMB_DATA_CTRL 0x0122
-+#define CCS_EMB_DATA_CTRL_RAW8_PACKING_FOR_RAW16 BIT(0)
-+#define CCS_EMB_DATA_CTRL_RAW10_PACKING_FOR_RAW20 BIT(1)
-+#define CCS_EMB_DATA_CTRL_RAW12_PACKING_FOR_RAW24 BIT(2)
-+#define CCS_R_GPIO_TRIG_MODE 0x0130
-+#define CCS_R_EXTCLK_FREQUENCY_MHZ (0x0136 | (CCS_FL_16BIT | CCS_FL_IREAL))
-+#define CCS_R_TEMP_SENSOR_CTRL 0x0138
-+#define CCS_TEMP_SENSOR_CTRL_ENABLE BIT(0)
-+#define CCS_R_TEMP_SENSOR_MODE 0x0139
-+#define CCS_R_TEMP_SENSOR_OUTPUT 0x013a
-+#define CCS_R_FINE_INTEGRATION_TIME (0x0200 | CCS_FL_16BIT)
-+#define CCS_R_COARSE_INTEGRATION_TIME (0x0202 | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_GAIN_CODE_GLOBAL (0x0204 | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_LINEAR_GAIN_GLOBAL (0x0206 | CCS_FL_16BIT)
-+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_GLOBAL (0x0208 | CCS_FL_16BIT)
-+#define CCS_R_DIGITAL_GAIN_GLOBAL (0x020e | CCS_FL_16BIT)
-+#define CCS_R_SHORT_ANALOG_GAIN_GLOBAL (0x0216 | CCS_FL_16BIT)
-+#define CCS_R_SHORT_DIGITAL_GAIN_GLOBAL (0x0218 | CCS_FL_16BIT)
-+#define CCS_R_HDR_MODE 0x0220
-+#define CCS_HDR_MODE_ENABLED BIT(0)
-+#define CCS_HDR_MODE_SEPARATE_ANALOG_GAIN BIT(1)
-+#define CCS_HDR_MODE_UPSCALING BIT(2)
-+#define CCS_HDR_MODE_RESET_SYNC BIT(3)
-+#define CCS_HDR_MODE_TIMING_MODE BIT(4)
-+#define CCS_HDR_MODE_EXPOSURE_CTRL_DIRECT BIT(5)
-+#define CCS_HDR_MODE_SEPARATE_DIGITAL_GAIN BIT(6)
-+#define CCS_R_HDR_RESOLUTION_REDUCTION 0x0221
-+#define CCS_HDR_RESOLUTION_REDUCTION_ROW_SHIFT 0U
-+#define CCS_HDR_RESOLUTION_REDUCTION_ROW_MASK 0xf
-+#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_SHIFT 4U
-+#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_MASK 0xf0
-+#define CCS_R_EXPOSURE_RATIO 0x0222
-+#define CCS_R_HDR_INTERNAL_BIT_DEPTH 0x0223
-+#define CCS_R_DIRECT_SHORT_INTEGRATION_TIME (0x0224 | CCS_FL_16BIT)
-+#define CCS_R_SHORT_ANALOG_LINEAR_GAIN_GLOBAL (0x0226 | CCS_FL_16BIT)
-+#define CCS_R_SHORT_ANALOG_EXPONENTIAL_GAIN_GLOBAL (0x0228 | CCS_FL_16BIT)
-+#define CCS_R_VT_PIX_CLK_DIV (0x0300 | CCS_FL_16BIT)
-+#define CCS_R_VT_SYS_CLK_DIV (0x0302 | CCS_FL_16BIT)
-+#define CCS_R_PRE_PLL_CLK_DIV (0x0304 | CCS_FL_16BIT)
-+#define CCS_R_PLL_MULTIPLIER (0x0306 | CCS_FL_16BIT)
-+#define CCS_R_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT)
-+#define CCS_R_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT)
-+#define CCS_R_OP_PRE_PLL_CLK_DIV (0x030c | CCS_FL_16BIT)
-+#define CCS_R_OP_PLL_MULTIPLIER (0x031e | CCS_FL_16BIT)
-+#define CCS_R_PLL_MODE 0x0310
-+#define CCS_PLL_MODE_SHIFT 0U
-+#define CCS_PLL_MODE_MASK 0x1
-+#define CCS_PLL_MODE_SINGLE 0U
-+#define CCS_PLL_MODE_DUAL 1U
-+#define CCS_R_OP_PIX_CLK_DIV_REV (0x0312 | CCS_FL_16BIT)
-+#define CCS_R_OP_SYS_CLK_DIV_REV (0x0314 | CCS_FL_16BIT)
-+#define CCS_R_FRAME_LENGTH_LINES (0x0340 | CCS_FL_16BIT)
-+#define CCS_R_LINE_LENGTH_PCK (0x0342 | CCS_FL_16BIT)
-+#define CCS_R_X_ADDR_START (0x0344 | CCS_FL_16BIT)
-+#define CCS_R_Y_ADDR_START (0x0346 | CCS_FL_16BIT)
-+#define CCS_R_X_ADDR_END (0x0348 | CCS_FL_16BIT)
-+#define CCS_R_Y_ADDR_END (0x034a | CCS_FL_16BIT)
-+#define CCS_R_X_OUTPUT_SIZE (0x034c | CCS_FL_16BIT)
-+#define CCS_R_Y_OUTPUT_SIZE (0x034e | CCS_FL_16BIT)
-+#define CCS_R_FRAME_LENGTH_CTRL 0x0350
-+#define CCS_FRAME_LENGTH_CTRL_AUTOMATIC BIT(0)
-+#define CCS_R_TIMING_MODE_CTRL 0x0352
-+#define CCS_TIMING_MODE_CTRL_MANUAL_READOUT BIT(0)
-+#define CCS_TIMING_MODE_CTRL_DELAYED_EXPOSURE BIT(1)
-+#define CCS_R_START_READOUT_RS 0x0353
-+#define CCS_START_READOUT_RS_MANUAL_READOUT_START BIT(0)
-+#define CCS_R_FRAME_MARGIN (0x0354 | CCS_FL_16BIT)
-+#define CCS_R_X_EVEN_INC (0x0380 | CCS_FL_16BIT)
-+#define CCS_R_X_ODD_INC (0x0382 | CCS_FL_16BIT)
-+#define CCS_R_Y_EVEN_INC (0x0384 | CCS_FL_16BIT)
-+#define CCS_R_Y_ODD_INC (0x0386 | CCS_FL_16BIT)
-+#define CCS_R_MONOCHROME_EN 0x0390
-+#define CCS_MONOCHROME_EN_ENABLED 0U
-+#define CCS_R_SCALING_MODE (0x0400 | CCS_FL_16BIT)
-+#define CCS_SCALING_MODE_NO_SCALING 0U
-+#define CCS_SCALING_MODE_HORIZONTAL 1U
-+#define CCS_R_SCALE_M (0x0404 | CCS_FL_16BIT)
-+#define CCS_R_SCALE_N (0x0406 | CCS_FL_16BIT)
-+#define CCS_R_DIGITAL_CROP_X_OFFSET (0x0408 | CCS_FL_16BIT)
-+#define CCS_R_DIGITAL_CROP_Y_OFFSET (0x040a | CCS_FL_16BIT)
-+#define CCS_R_DIGITAL_CROP_IMAGE_WIDTH (0x040c | CCS_FL_16BIT)
-+#define CCS_R_DIGITAL_CROP_IMAGE_HEIGHT (0x040e | CCS_FL_16BIT)
-+#define CCS_R_COMPRESSION_MODE (0x0500 | CCS_FL_16BIT)
-+#define CCS_COMPRESSION_MODE_NONE 0U
-+#define CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE 1U
-+#define CCS_R_TEST_PATTERN_MODE (0x0600 | CCS_FL_16BIT)
-+#define CCS_TEST_PATTERN_MODE_NONE 0U
-+#define CCS_TEST_PATTERN_MODE_SOLID_COLOR 1U
-+#define CCS_TEST_PATTERN_MODE_COLOR_BARS 2U
-+#define CCS_TEST_PATTERN_MODE_FADE_TO_GREY 3U
-+#define CCS_TEST_PATTERN_MODE_PN9 4U
-+#define CCS_TEST_PATTERN_MODE_COLOR_TILE 5U
-+#define CCS_R_TEST_DATA_RED (0x0602 | CCS_FL_16BIT)
-+#define CCS_R_TEST_DATA_GREENR (0x0604 | CCS_FL_16BIT)
-+#define CCS_R_TEST_DATA_BLUE (0x0606 | CCS_FL_16BIT)
-+#define CCS_R_TEST_DATA_GREENB (0x0608 | CCS_FL_16BIT)
-+#define CCS_R_VALUE_STEP_SIZE_SMOOTH 0x060a
-+#define CCS_R_VALUE_STEP_SIZE_QUANTISED 0x060b
-+#define CCS_R_TCLK_POST 0x0800
-+#define CCS_R_THS_PREPARE 0x0801
-+#define CCS_R_THS_ZERO_MIN 0x0802
-+#define CCS_R_THS_TRAIL 0x0803
-+#define CCS_R_TCLK_TRAIL_MIN 0x0804
-+#define CCS_R_TCLK_PREPARE 0x0805
-+#define CCS_R_TCLK_ZERO 0x0806
-+#define CCS_R_TLPX 0x0807
-+#define CCS_R_PHY_CTRL 0x0808
-+#define CCS_PHY_CTRL_AUTO 0U
-+#define CCS_PHY_CTRL_UI 1U
-+#define CCS_PHY_CTRL_MANUAL 2U
-+#define CCS_R_TCLK_POST_EX (0x080a | CCS_FL_16BIT)
-+#define CCS_R_THS_PREPARE_EX (0x080c | CCS_FL_16BIT)
-+#define CCS_R_THS_ZERO_MIN_EX (0x080e | CCS_FL_16BIT)
-+#define CCS_R_THS_TRAIL_EX (0x0810 | CCS_FL_16BIT)
-+#define CCS_R_TCLK_TRAIL_MIN_EX (0x0812 | CCS_FL_16BIT)
-+#define CCS_R_TCLK_PREPARE_EX (0x0814 | CCS_FL_16BIT)
-+#define CCS_R_TCLK_ZERO_EX (0x0816 | CCS_FL_16BIT)
-+#define CCS_R_TLPX_EX (0x0818 | CCS_FL_16BIT)
-+#define CCS_R_REQUESTED_LINK_RATE (0x0820 | CCS_FL_32BIT)
-+#define CCS_R_DPHY_EQUALIZATION_MODE 0x0824
-+#define CCS_DPHY_EQUALIZATION_MODE_EQ2 BIT(0)
-+#define CCS_R_PHY_EQUALIZATION_CTRL 0x0825
-+#define CCS_PHY_EQUALIZATION_CTRL_ENABLE BIT(0)
-+#define CCS_R_DPHY_PREAMBLE_CTRL 0x0826
-+#define CCS_DPHY_PREAMBLE_CTRL_ENABLE BIT(0)
-+#define CCS_R_DPHY_PREAMBLE_LENGTH 0x0826
-+#define CCS_R_PHY_SSC_CTRL 0x0828
-+#define CCS_PHY_SSC_CTRL_ENABLE BIT(0)
-+#define CCS_R_MANUAL_LP_CTRL 0x0829
-+#define CCS_MANUAL_LP_CTRL_ENABLE BIT(0)
-+#define CCS_R_TWAKEUP 0x082a
-+#define CCS_R_TINIT 0x082b
-+#define CCS_R_THS_EXIT 0x082c
-+#define CCS_R_THS_EXIT_EX (0x082e | CCS_FL_16BIT)
-+#define CCS_R_PHY_PERIODIC_CALIBRATION_CTRL 0x0830
-+#define CCS_PHY_PERIODIC_CALIBRATION_CTRL_FRAME_BLANKING BIT(0)
-+#define CCS_R_PHY_PERIODIC_CALIBRATION_INTERVAL 0x0831
-+#define CCS_R_PHY_INIT_CALIBRATION_CTRL 0x0832
-+#define CCS_PHY_INIT_CALIBRATION_CTRL_STREAM_START BIT(0)
-+#define CCS_R_DPHY_CALIBRATION_MODE 0x0833
-+#define CCS_DPHY_CALIBRATION_MODE_ALSO_ALTERNATE BIT(0)
-+#define CCS_R_CPHY_CALIBRATION_MODE 0x0834
-+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_1 0U
-+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_2 1U
-+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_3 2U
-+#define CCS_R_T3_CALPREAMBLE_LENGTH 0x0835
-+#define CCS_R_T3_CALPREAMBLE_LENGTH_PER 0x0836
-+#define CCS_R_T3_CALALTSEQ_LENGTH 0x0837
-+#define CCS_R_T3_CALALTSEQ_LENGTH_PER 0x0838
-+#define CCS_R_FM2_INIT_SEED (0x083a | CCS_FL_16BIT)
-+#define CCS_R_T3_CALUDEFSEQ_LENGTH (0x083c | CCS_FL_16BIT)
-+#define CCS_R_T3_CALUDEFSEQ_LENGTH_PER (0x083e | CCS_FL_16BIT)
-+#define CCS_R_TGR_PREAMBLE_LENGTH 0x0841
-+#define CCS_TGR_PREAMBLE_LENGTH_PREAMABLE_PROG_SEQ BIT(7)
-+#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_SHIFT 0U
-+#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_MASK 0x3f
-+#define CCS_R_TGR_POST_LENGTH 0x0842
-+#define CCS_TGR_POST_LENGTH_POST_LENGTH_SHIFT 0U
-+#define CCS_TGR_POST_LENGTH_POST_LENGTH_MASK 0x1f
-+#define CCS_R_TGR_PREAMBLE_PROG_SEQUENCE(n2) (0x0843 + (n2))
-+#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MIN_N2 0U
-+#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MAX_N2 6U
-+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_SHIFT 3U
-+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_MASK 0x38
-+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_SHIFT 0U
-+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_MASK 0x7
-+#define CCS_R_T3_PREPARE (0x084e | CCS_FL_16BIT)
-+#define CCS_R_T3_LPX (0x0850 | CCS_FL_16BIT)
-+#define CCS_R_ALPS_CTRL 0x085a
-+#define CCS_ALPS_CTRL_LVLP_DPHY BIT(0)
-+#define CCS_ALPS_CTRL_LVLP_CPHY BIT(1)
-+#define CCS_ALPS_CTRL_ALP_CPHY BIT(2)
-+#define CCS_R_TX_REG_CSI_EPD_EN_SSP_CPHY (0x0860 | CCS_FL_16BIT)
-+#define CCS_R_TX_REG_CSI_EPD_OP_SLP_CPHY (0x0862 | CCS_FL_16BIT)
-+#define CCS_R_TX_REG_CSI_EPD_EN_SSP_DPHY (0x0864 | CCS_FL_16BIT)
-+#define CCS_R_TX_REG_CSI_EPD_OP_SLP_DPHY (0x0866 | CCS_FL_16BIT)
-+#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_CPHY 0x0868
-+#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_DPHY 0x0869
-+#define CCS_R_SCRAMBLING_CTRL 0x0870
-+#define CCS_SCRAMBLING_CTRL_ENABLED BIT(0)
-+#define CCS_SCRAMBLING_CTRL_SHIFT 2U
-+#define CCS_SCRAMBLING_CTRL_MASK 0xc
-+#define CCS_SCRAMBLING_CTRL_1_SEED_CPHY 0U
-+#define CCS_SCRAMBLING_CTRL_4_SEED_CPHY 3U
-+#define CCS_R_LANE_SEED_VALUE(seed, lane) ((0x0872 | CCS_FL_16BIT) + (seed) * 16 + (lane) * 2)
-+#define CCS_LIM_LANE_SEED_VALUE_MIN_SEED 0U
-+#define CCS_LIM_LANE_SEED_VALUE_MAX_SEED 3U
-+#define CCS_LIM_LANE_SEED_VALUE_MIN_LANE 0U
-+#define CCS_LIM_LANE_SEED_VALUE_MAX_LANE 7U
-+#define CCS_R_TX_USL_REV_ENTRY (0x08c0 | CCS_FL_16BIT)
-+#define CCS_R_TX_USL_REV_CLOCK_COUNTER (0x08c2 | CCS_FL_16BIT)
-+#define CCS_R_TX_USL_REV_LP_COUNTER (0x08c4 | CCS_FL_16BIT)
-+#define CCS_R_TX_USL_REV_FRAME_COUNTER (0x08c6 | CCS_FL_16BIT)
-+#define CCS_R_TX_USL_REV_CHRONOLOGICAL_TIMER (0x08c8 | CCS_FL_16BIT)
-+#define CCS_R_TX_USL_FWD_ENTRY (0x08ca | CCS_FL_16BIT)
-+#define CCS_R_TX_USL_GPIO (0x08cc | CCS_FL_16BIT)
-+#define CCS_R_TX_USL_OPERATION (0x08ce | CCS_FL_16BIT)
-+#define CCS_TX_USL_OPERATION_RESET BIT(0)
-+#define CCS_R_TX_USL_ALP_CTRL (0x08d0 | CCS_FL_16BIT)
-+#define CCS_TX_USL_ALP_CTRL_CLOCK_PAUSE BIT(0)
-+#define CCS_R_TX_USL_APP_BTA_ACK_TIMEOUT (0x08d2 | CCS_FL_16BIT)
-+#define CCS_R_TX_USL_SNS_BTA_ACK_TIMEOUT (0x08d2 | CCS_FL_16BIT)
-+#define CCS_R_USL_CLOCK_MODE_D_CTRL 0x08d2
-+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_STANDBY BIT(0)
-+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_VBLANK BIT(1)
-+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_HBLANK BIT(2)
-+#define CCS_R_BINNING_MODE 0x0900
-+#define CCS_R_BINNING_TYPE 0x0901
-+#define CCS_R_BINNING_WEIGHTING 0x0902
-+#define CCS_R_DATA_TRANSFER_IF_1_CTRL 0x0a00
-+#define CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE BIT(0)
-+#define CCS_DATA_TRANSFER_IF_1_CTRL_WRITE BIT(1)
-+#define CCS_DATA_TRANSFER_IF_1_CTRL_CLEAR_ERROR BIT(2)
-+#define CCS_R_DATA_TRANSFER_IF_1_STATUS 0x0a01
-+#define CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY BIT(0)
-+#define CCS_DATA_TRANSFER_IF_1_STATUS_WRITE_IF_READY BIT(1)
-+#define CCS_DATA_TRANSFER_IF_1_STATUS_DATA_CORRUPTED BIT(2)
-+#define CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE BIT(3)
-+#define CCS_R_DATA_TRANSFER_IF_1_PAGE_SELECT 0x0a02
-+#define CCS_R_DATA_TRANSFER_IF_1_DATA(p) (0x0a04 + (p))
-+#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MIN_P 0U
-+#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P 63U
-+#define CCS_R_SHADING_CORRECTION_EN 0x0b00
-+#define CCS_SHADING_CORRECTION_EN_ENABLE BIT(0)
-+#define CCS_R_LUMINANCE_CORRECTION_LEVEL 0x0b01
-+#define CCS_R_GREEN_IMBALANCE_FILTER_EN 0x0b02
-+#define CCS_GREEN_IMBALANCE_FILTER_EN_ENABLE BIT(0)
-+#define CCS_R_MAPPED_DEFECT_CORRECT_EN 0x0b05
-+#define CCS_MAPPED_DEFECT_CORRECT_EN_ENABLE BIT(0)
-+#define CCS_R_SINGLE_DEFECT_CORRECT_EN 0x0b06
-+#define CCS_SINGLE_DEFECT_CORRECT_EN_ENABLE BIT(0)
-+#define CCS_R_DYNAMIC_COUPLET_CORRECT_EN 0x0b08
-+#define CCS_DYNAMIC_COUPLET_CORRECT_EN_ENABLE BIT(0)
-+#define CCS_R_COMBINED_DEFECT_CORRECT_EN 0x0b0a
-+#define CCS_COMBINED_DEFECT_CORRECT_EN_ENABLE BIT(0)
-+#define CCS_R_MODULE_SPECIFIC_CORRECTION_EN 0x0b0c
-+#define CCS_MODULE_SPECIFIC_CORRECTION_EN_ENABLE BIT(0)
-+#define CCS_R_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN 0x0b13
-+#define CCS_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN_ENABLE BIT(0)
-+#define CCS_R_NF_CTRL 0x0b15
-+#define CCS_NF_CTRL_LUMA BIT(0)
-+#define CCS_NF_CTRL_CHROMA BIT(1)
-+#define CCS_NF_CTRL_COMBINED BIT(2)
-+#define CCS_R_OB_READOUT_CONTROL 0x0b30
-+#define CCS_OB_READOUT_CONTROL_ENABLE BIT(0)
-+#define CCS_OB_READOUT_CONTROL_INTERLEAVING BIT(1)
-+#define CCS_R_OB_VIRTUAL_CHANNEL 0x0b31
-+#define CCS_R_OB_DT 0x0b32
-+#define CCS_R_OB_DATA_FORMAT 0x0b33
-+#define CCS_R_COLOR_TEMPERATURE (0x0b8c | CCS_FL_16BIT)
-+#define CCS_R_ABSOLUTE_GAIN_GREENR (0x0b8e | CCS_FL_16BIT)
-+#define CCS_R_ABSOLUTE_GAIN_RED (0x0b90 | CCS_FL_16BIT)
-+#define CCS_R_ABSOLUTE_GAIN_BLUE (0x0b92 | CCS_FL_16BIT)
-+#define CCS_R_ABSOLUTE_GAIN_GREENB (0x0b94 | CCS_FL_16BIT)
-+#define CCS_R_CFA_CONVERSION_CTRL 0x0ba0
-+#define CCS_CFA_CONVERSION_CTRL_BAYER_CONVERSION_ENABLE BIT(0)
-+#define CCS_R_FLASH_STROBE_ADJUSTMENT 0x0c12
-+#define CCS_R_FLASH_STROBE_START_POINT (0x0c14 | CCS_FL_16BIT)
-+#define CCS_R_TFLASH_STROBE_DELAY_RS_CTRL (0x0c16 | CCS_FL_16BIT)
-+#define CCS_R_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL (0x0c18 | CCS_FL_16BIT)
-+#define CCS_R_FLASH_MODE_RS 0x0c1a
-+#define CCS_FLASH_MODE_RS_CONTINUOUS BIT(0)
-+#define CCS_FLASH_MODE_RS_TRUNCATE BIT(1)
-+#define CCS_FLASH_MODE_RS_ASYNC BIT(3)
-+#define CCS_R_FLASH_TRIGGER_RS 0x0c1b
-+#define CCS_R_FLASH_STATUS 0x0c1c
-+#define CCS_FLASH_STATUS_RETIMED BIT(0)
-+#define CCS_R_SA_STROBE_MODE 0x0c1d
-+#define CCS_SA_STROBE_MODE_CONTINUOUS BIT(0)
-+#define CCS_SA_STROBE_MODE_TRUNCATE BIT(1)
-+#define CCS_SA_STROBE_MODE_ASYNC BIT(3)
-+#define CCS_SA_STROBE_MODE_ADJUST_EDGE BIT(4)
-+#define CCS_R_SA_STROBE_START_POINT (0x0c1e | CCS_FL_16BIT)
-+#define CCS_R_TSA_STROBE_DELAY_CTRL (0x0c20 | CCS_FL_16BIT)
-+#define CCS_R_TSA_STROBE_WIDTH_CTRL (0x0c22 | CCS_FL_16BIT)
-+#define CCS_R_SA_STROBE_TRIGGER 0x0c24
-+#define CCS_R_SA_STROBE_STATUS 0x0c25
-+#define CCS_SA_STROBE_STATUS_RETIMED BIT(0)
-+#define CCS_R_TSA_STROBE_RE_DELAY_CTRL (0x0c30 | CCS_FL_16BIT)
-+#define CCS_R_TSA_STROBE_FE_DELAY_CTRL (0x0c32 | CCS_FL_16BIT)
-+#define CCS_R_PDAF_CTRL (0x0d00 | CCS_FL_16BIT)
-+#define CCS_PDAF_CTRL_ENABLE BIT(0)
-+#define CCS_PDAF_CTRL_PROCESSED BIT(1)
-+#define CCS_PDAF_CTRL_INTERLEAVED BIT(2)
-+#define CCS_PDAF_CTRL_VISIBLE_PDAF_CORRECTION BIT(3)
-+#define CCS_R_PDAF_VC 0x0d02
-+#define CCS_R_PDAF_DT 0x0d03
-+#define CCS_R_PD_X_ADDR_START (0x0d04 | CCS_FL_16BIT)
-+#define CCS_R_PD_Y_ADDR_START (0x0d06 | CCS_FL_16BIT)
-+#define CCS_R_PD_X_ADDR_END (0x0d08 | CCS_FL_16BIT)
-+#define CCS_R_PD_Y_ADDR_END (0x0d0a | CCS_FL_16BIT)
-+#define CCS_R_BRACKETING_LUT_CTRL 0x0e00
-+#define CCS_R_BRACKETING_LUT_MODE 0x0e01
-+#define CCS_BRACKETING_LUT_MODE_CONTINUE_STREAMING BIT(0)
-+#define CCS_BRACKETING_LUT_MODE_LOOP_MODE BIT(1)
-+#define CCS_R_BRACKETING_LUT_ENTRY_CTRL 0x0e02
-+#define CCS_R_BRACKETING_LUT_FRAME(n) (0x0e10 + (n))
-+#define CCS_LIM_BRACKETING_LUT_FRAME_MIN_N 0U
-+#define CCS_LIM_BRACKETING_LUT_FRAME_MAX_N 239U
-+#define CCS_R_INTEGRATION_TIME_CAPABILITY (0x1000 | CCS_FL_16BIT)
-+#define CCS_INTEGRATION_TIME_CAPABILITY_FINE BIT(0)
-+#define CCS_R_COARSE_INTEGRATION_TIME_MIN (0x1004 | CCS_FL_16BIT)
-+#define CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN (0x1006 | CCS_FL_16BIT)
-+#define CCS_R_FINE_INTEGRATION_TIME_MIN (0x1008 | CCS_FL_16BIT)
-+#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN (0x100a | CCS_FL_16BIT)
-+#define CCS_R_DIGITAL_GAIN_CAPABILITY 0x1081
-+#define CCS_DIGITAL_GAIN_CAPABILITY_NONE 0U
-+#define CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL 2U
-+#define CCS_R_DIGITAL_GAIN_MIN (0x1084 | CCS_FL_16BIT)
-+#define CCS_R_DIGITAL_GAIN_MAX (0x1086 | CCS_FL_16BIT)
-+#define CCS_R_DIGITAL_GAIN_STEP_SIZE (0x1088 | CCS_FL_16BIT)
-+#define CCS_R_PEDESTAL_CAPABILITY 0x10e0
-+#define CCS_R_ADC_CAPABILITY 0x10f0
-+#define CCS_ADC_CAPABILITY_BIT_DEPTH_CTRL BIT(0)
-+#define CCS_R_ADC_BIT_DEPTH_CAPABILITY (0x10f4 | CCS_FL_32BIT)
-+#define CCS_R_MIN_EXT_CLK_FREQ_MHZ (0x1100 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_EXT_CLK_FREQ_MHZ (0x1104 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MIN_PRE_PLL_CLK_DIV (0x1108 | CCS_FL_16BIT)
-+#define CCS_R_MAX_PRE_PLL_CLK_DIV (0x110a | CCS_FL_16BIT)
-+#define CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ (0x110c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ (0x1110 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MIN_PLL_MULTIPLIER (0x1114 | CCS_FL_16BIT)
-+#define CCS_R_MAX_PLL_MULTIPLIER (0x1116 | CCS_FL_16BIT)
-+#define CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ (0x1118 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ (0x111c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MIN_VT_SYS_CLK_DIV (0x1120 | CCS_FL_16BIT)
-+#define CCS_R_MAX_VT_SYS_CLK_DIV (0x1122 | CCS_FL_16BIT)
-+#define CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ (0x1124 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ (0x1128 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ (0x112c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ (0x1130 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MIN_VT_PIX_CLK_DIV (0x1134 | CCS_FL_16BIT)
-+#define CCS_R_MAX_VT_PIX_CLK_DIV (0x1136 | CCS_FL_16BIT)
-+#define CCS_R_CLOCK_CALCULATION 0x1138
-+#define CCS_CLOCK_CALCULATION_LANE_SPEED BIT(0)
-+#define CCS_CLOCK_CALCULATION_LINK_DECOUPLED BIT(1)
-+#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR BIT(2)
-+#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR BIT(3)
-+#define CCS_R_NUM_OF_VT_LANES 0x1139
-+#define CCS_R_NUM_OF_OP_LANES 0x113a
-+#define CCS_R_OP_BITS_PER_LANE 0x113b
-+#define CCS_R_MIN_FRAME_LENGTH_LINES (0x1140 | CCS_FL_16BIT)
-+#define CCS_R_MAX_FRAME_LENGTH_LINES (0x1142 | CCS_FL_16BIT)
-+#define CCS_R_MIN_LINE_LENGTH_PCK (0x1144 | CCS_FL_16BIT)
-+#define CCS_R_MAX_LINE_LENGTH_PCK (0x1146 | CCS_FL_16BIT)
-+#define CCS_R_MIN_LINE_BLANKING_PCK (0x1148 | CCS_FL_16BIT)
-+#define CCS_R_MIN_FRAME_BLANKING_LINES (0x114a | CCS_FL_16BIT)
-+#define CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE 0x114c
-+#define CCS_R_TIMING_MODE_CAPABILITY 0x114d
-+#define CCS_TIMING_MODE_CAPABILITY_AUTO_FRAME_LENGTH BIT(0)
-+#define CCS_TIMING_MODE_CAPABILITY_ROLLING_SHUTTER_MANUAL_READOUT BIT(2)
-+#define CCS_TIMING_MODE_CAPABILITY_DELAYED_EXPOSURE_START BIT(3)
-+#define CCS_TIMING_MODE_CAPABILITY_MANUAL_EXPOSURE_EMBEDDED_DATA BIT(4)
-+#define CCS_R_FRAME_MARGIN_MAX_VALUE (0x114e | CCS_FL_16BIT)
-+#define CCS_R_FRAME_MARGIN_MIN_VALUE 0x1150
-+#define CCS_R_GAIN_DELAY_TYPE 0x1151
-+#define CCS_GAIN_DELAY_TYPE_FIXED 0U
-+#define CCS_GAIN_DELAY_TYPE_VARIABLE 1U
-+#define CCS_R_MIN_OP_SYS_CLK_DIV (0x1160 | CCS_FL_16BIT)
-+#define CCS_R_MAX_OP_SYS_CLK_DIV (0x1162 | CCS_FL_16BIT)
-+#define CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ (0x1164 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ (0x1168 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MIN_OP_PIX_CLK_DIV (0x116c | CCS_FL_16BIT)
-+#define CCS_R_MAX_OP_PIX_CLK_DIV (0x116e | CCS_FL_16BIT)
-+#define CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ (0x1170 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ (0x1174 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_X_ADDR_MIN (0x1180 | CCS_FL_16BIT)
-+#define CCS_R_Y_ADDR_MIN (0x1182 | CCS_FL_16BIT)
-+#define CCS_R_X_ADDR_MAX (0x1184 | CCS_FL_16BIT)
-+#define CCS_R_Y_ADDR_MAX (0x1186 | CCS_FL_16BIT)
-+#define CCS_R_MIN_X_OUTPUT_SIZE (0x1188 | CCS_FL_16BIT)
-+#define CCS_R_MIN_Y_OUTPUT_SIZE (0x118a | CCS_FL_16BIT)
-+#define CCS_R_MAX_X_OUTPUT_SIZE (0x118c | CCS_FL_16BIT)
-+#define CCS_R_MAX_Y_OUTPUT_SIZE (0x118e | CCS_FL_16BIT)
-+#define CCS_R_X_ADDR_START_DIV_CONSTANT 0x1190
-+#define CCS_R_Y_ADDR_START_DIV_CONSTANT 0x1191
-+#define CCS_R_X_ADDR_END_DIV_CONSTANT 0x1192
-+#define CCS_R_Y_ADDR_END_DIV_CONSTANT 0x1193
-+#define CCS_R_X_SIZE_DIV 0x1194
-+#define CCS_R_Y_SIZE_DIV 0x1195
-+#define CCS_R_X_OUTPUT_DIV 0x1196
-+#define CCS_R_Y_OUTPUT_DIV 0x1197
-+#define CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT 0x1198
-+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_PIX_ADDR BIT(0)
-+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_OUTPUT_RES BIT(1)
-+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_CROP_NO_PAD BIT(2)
-+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_SIZE_LANE_DEP BIT(3)
-+#define CCS_R_MIN_OP_PRE_PLL_CLK_DIV (0x11a0 | CCS_FL_16BIT)
-+#define CCS_R_MAX_OP_PRE_PLL_CLK_DIV (0x11a2 | CCS_FL_16BIT)
-+#define CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ (0x11a4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ (0x11a8 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MIN_OP_PLL_MULTIPLIER (0x11ac | CCS_FL_16BIT)
-+#define CCS_R_MAX_OP_PLL_MULTIPLIER (0x11ae | CCS_FL_16BIT)
-+#define CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ (0x11b0 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ (0x11b4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_CLOCK_TREE_PLL_CAPABILITY 0x11b8
-+#define CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL BIT(0)
-+#define CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL BIT(1)
-+#define CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER BIT(2)
-+#define CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV BIT(3)
-+#define CCS_R_CLOCK_CAPA_TYPE_CAPABILITY 0x11b9
-+#define CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL BIT(0)
-+#define CCS_R_MIN_EVEN_INC (0x11c0 | CCS_FL_16BIT)
-+#define CCS_R_MIN_ODD_INC (0x11c2 | CCS_FL_16BIT)
-+#define CCS_R_MAX_EVEN_INC (0x11c4 | CCS_FL_16BIT)
-+#define CCS_R_MAX_ODD_INC (0x11c6 | CCS_FL_16BIT)
-+#define CCS_R_AUX_SUBSAMP_CAPABILITY 0x11c8
-+#define CCS_AUX_SUBSAMP_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
-+#define CCS_R_AUX_SUBSAMP_MONO_CAPABILITY 0x11c9
-+#define CCS_AUX_SUBSAMP_MONO_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
-+#define CCS_R_MONOCHROME_CAPABILITY 0x11ca
-+#define CCS_MONOCHROME_CAPABILITY_INC_ODD 0U
-+#define CCS_MONOCHROME_CAPABILITY_INC_EVEN 1U
-+#define CCS_R_PIXEL_READOUT_CAPABILITY 0x11cb
-+#define CCS_PIXEL_READOUT_CAPABILITY_BAYER 0U
-+#define CCS_PIXEL_READOUT_CAPABILITY_MONOCHROME 1U
-+#define CCS_PIXEL_READOUT_CAPABILITY_BAYER_AND_MONO 2U
-+#define CCS_R_MIN_EVEN_INC_MONO (0x11cc | CCS_FL_16BIT)
-+#define CCS_R_MAX_EVEN_INC_MONO (0x11ce | CCS_FL_16BIT)
-+#define CCS_R_MIN_ODD_INC_MONO (0x11d0 | CCS_FL_16BIT)
-+#define CCS_R_MAX_ODD_INC_MONO (0x11d2 | CCS_FL_16BIT)
-+#define CCS_R_MIN_EVEN_INC_BC2 (0x11d4 | CCS_FL_16BIT)
-+#define CCS_R_MAX_EVEN_INC_BC2 (0x11d6 | CCS_FL_16BIT)
-+#define CCS_R_MIN_ODD_INC_BC2 (0x11d8 | CCS_FL_16BIT)
-+#define CCS_R_MAX_ODD_INC_BC2 (0x11da | CCS_FL_16BIT)
-+#define CCS_R_MIN_EVEN_INC_MONO_BC2 (0x11dc | CCS_FL_16BIT)
-+#define CCS_R_MAX_EVEN_INC_MONO_BC2 (0x11de | CCS_FL_16BIT)
-+#define CCS_R_MIN_ODD_INC_MONO_BC2 (0x11f0 | CCS_FL_16BIT)
-+#define CCS_R_MAX_ODD_INC_MONO_BC2 (0x11f2 | CCS_FL_16BIT)
-+#define CCS_R_SCALING_CAPABILITY (0x1200 | CCS_FL_16BIT)
-+#define CCS_SCALING_CAPABILITY_NONE 0U
-+#define CCS_SCALING_CAPABILITY_HORIZONTAL 1U
-+#define CCS_SCALING_CAPABILITY_RESERVED 2U
-+#define CCS_R_SCALER_M_MIN (0x1204 | CCS_FL_16BIT)
-+#define CCS_R_SCALER_M_MAX (0x1206 | CCS_FL_16BIT)
-+#define CCS_R_SCALER_N_MIN (0x1208 | CCS_FL_16BIT)
-+#define CCS_R_SCALER_N_MAX (0x120a | CCS_FL_16BIT)
-+#define CCS_R_DIGITAL_CROP_CAPABILITY 0x120e
-+#define CCS_DIGITAL_CROP_CAPABILITY_NONE 0U
-+#define CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1U
-+#define CCS_R_HDR_CAPABILITY_1 0x1210
-+#define CCS_HDR_CAPABILITY_1_2X2_BINNING BIT(0)
-+#define CCS_HDR_CAPABILITY_1_COMBINED_ANALOG_GAIN BIT(1)
-+#define CCS_HDR_CAPABILITY_1_SEPARATE_ANALOG_GAIN BIT(2)
-+#define CCS_HDR_CAPABILITY_1_UPSCALING BIT(3)
-+#define CCS_HDR_CAPABILITY_1_RESET_SYNC BIT(4)
-+#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_TIMING BIT(5)
-+#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_SYNTHESIS BIT(6)
-+#define CCS_R_MIN_HDR_BIT_DEPTH 0x1211
-+#define CCS_R_HDR_RESOLUTION_SUB_TYPES 0x1212
-+#define CCS_R_HDR_RESOLUTION_SUB_TYPE(n) (0x1213 + (n))
-+#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MIN_N 0U
-+#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MAX_N 1U
-+#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_SHIFT 0U
-+#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_MASK 0xf
-+#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_SHIFT 4U
-+#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_MASK 0xf0
-+#define CCS_R_HDR_CAPABILITY_2 0x121b
-+#define CCS_HDR_CAPABILITY_2_COMBINED_DIGITAL_GAIN BIT(0)
-+#define CCS_HDR_CAPABILITY_2_SEPARATE_DIGITAL_GAIN BIT(1)
-+#define CCS_HDR_CAPABILITY_2_TIMING_MODE BIT(3)
-+#define CCS_HDR_CAPABILITY_2_SYNTHESIS_MODE BIT(4)
-+#define CCS_R_MAX_HDR_BIT_DEPTH 0x121c
-+#define CCS_R_USL_SUPPORT_CAPABILITY 0x1230
-+#define CCS_USL_SUPPORT_CAPABILITY_CLOCK_TREE BIT(0)
-+#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_TREE BIT(1)
-+#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_CALC BIT(2)
-+#define CCS_R_USL_CLOCK_MODE_D_CAPABILITY 0x1231
-+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_STANDBY BIT(0)
-+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_VBLANK BIT(1)
-+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_HBLANK BIT(2)
-+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_STANDBY BIT(3)
-+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_VBLANK BIT(4)
-+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_HBLANK BIT(5)
-+#define CCS_R_MIN_OP_SYS_CLK_DIV_REV 0x1234
-+#define CCS_R_MAX_OP_SYS_CLK_DIV_REV 0x1236
-+#define CCS_R_MIN_OP_PIX_CLK_DIV_REV 0x1238
-+#define CCS_R_MAX_OP_PIX_CLK_DIV_REV 0x123a
-+#define CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ (0x123c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ (0x1240 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ (0x1244 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ (0x1248 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
-+#define CCS_R_MAX_BITRATE_REV_D_MODE_MBPS (0x124c | (CCS_FL_32BIT | CCS_FL_IREAL))
-+#define CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS (0x1250 | (CCS_FL_32BIT | CCS_FL_IREAL))
-+#define CCS_R_COMPRESSION_CAPABILITY 0x1300
-+#define CCS_COMPRESSION_CAPABILITY_DPCM_PCM_SIMPLE BIT(0)
-+#define CCS_R_TEST_MODE_CAPABILITY (0x1310 | CCS_FL_16BIT)
-+#define CCS_TEST_MODE_CAPABILITY_SOLID_COLOR BIT(0)
-+#define CCS_TEST_MODE_CAPABILITY_COLOR_BARS BIT(1)
-+#define CCS_TEST_MODE_CAPABILITY_FADE_TO_GREY BIT(2)
-+#define CCS_TEST_MODE_CAPABILITY_PN9 BIT(3)
-+#define CCS_TEST_MODE_CAPABILITY_COLOR_TILE BIT(5)
-+#define CCS_R_PN9_DATA_FORMAT1 0x1312
-+#define CCS_R_PN9_DATA_FORMAT2 0x1313
-+#define CCS_R_PN9_DATA_FORMAT3 0x1314
-+#define CCS_R_PN9_DATA_FORMAT4 0x1315
-+#define CCS_R_PN9_MISC_CAPABILITY 0x1316
-+#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_SHIFT 0U
-+#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_MASK 0x7
-+#define CCS_PN9_MISC_CAPABILITY_COMPRESSION BIT(3)
-+#define CCS_R_TEST_PATTERN_CAPABILITY 0x1317
-+#define CCS_TEST_PATTERN_CAPABILITY_NO_REPEAT BIT(1)
-+#define CCS_R_PATTERN_SIZE_DIV_M1 0x1318
-+#define CCS_R_FIFO_SUPPORT_CAPABILITY 0x1502
-+#define CCS_FIFO_SUPPORT_CAPABILITY_NONE 0U
-+#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING 1U
-+#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING 2U
-+#define CCS_R_PHY_CTRL_CAPABILITY 0x1600
-+#define CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL BIT(0)
-+#define CCS_PHY_CTRL_CAPABILITY_UI_PHY_CTL BIT(1)
-+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_1_CTL BIT(2)
-+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_2_CTL BIT(3)
-+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_CTL BIT(4)
-+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_1_CTL BIT(5)
-+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_2_CTL BIT(6)
-+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_CTL BIT(7)
-+#define CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY 0x1601
-+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
-+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
-+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
-+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
-+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
-+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
-+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
-+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
-+#define CCS_R_CSI_SIGNALING_MODE_CAPABILITY 0x1602
-+#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_DPHY BIT(2)
-+#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_CPHY BIT(3)
-+#define CCS_R_FAST_STANDBY_CAPABILITY 0x1603
-+#define CCS_FAST_STANDBY_CAPABILITY_NO_FRAME_TRUNCATION 0U
-+#define CCS_FAST_STANDBY_CAPABILITY_FRAME_TRUNCATION 1U
-+#define CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY 0x1604
-+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_CCI_ADDR_CHANGE BIT(0)
-+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_2ND_CCI_ADDR BIT(1)
-+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_SW_CHANGEABLE_2ND_CCI_ADDR BIT(2)
-+#define CCS_R_DATA_TYPE_CAPABILITY 0x1605
-+#define CCS_DATA_TYPE_CAPABILITY_DPCM_PROGRAMMABLE BIT(0)
-+#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_DT_PROGRAMMABLE BIT(1)
-+#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_VC_PROGRAMMABLE BIT(2)
-+#define CCS_DATA_TYPE_CAPABILITY_EXT_VC_RANGE BIT(3)
-+#define CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY 0x1606
-+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
-+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
-+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
-+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
-+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
-+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
-+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
-+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
-+#define CCS_R_EMB_DATA_CAPABILITY 0x1607
-+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW16 BIT(0)
-+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW20 BIT(1)
-+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW24 BIT(2)
-+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW16 BIT(3)
-+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW20 BIT(4)
-+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW24 BIT(5)
-+#define CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(n) ((0x1608 | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x32 + ((n) - 4) * 4))
-+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MIN_N 0U
-+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MAX_N 7U
-+#define CCS_R_TEMP_SENSOR_CAPABILITY 0x1618
-+#define CCS_TEMP_SENSOR_CAPABILITY_SUPPORTED BIT(0)
-+#define CCS_TEMP_SENSOR_CAPABILITY_CCS_FORMAT BIT(1)
-+#define CCS_TEMP_SENSOR_CAPABILITY_RESET_0X80 BIT(2)
-+#define CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(n) ((0x161a | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x30 + ((n) - 4) * 4))
-+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MIN_N 0U
-+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MAX_N 7U
-+#define CCS_R_DPHY_EQUALIZATION_CAPABILITY 0x162b
-+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
-+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ1 BIT(1)
-+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ2 BIT(2)
-+#define CCS_R_CPHY_EQUALIZATION_CAPABILITY 0x162c
-+#define CCS_CPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
-+#define CCS_R_DPHY_PREAMBLE_CAPABILITY 0x162d
-+#define CCS_DPHY_PREAMBLE_CAPABILITY_PREAMBLE_SEQ_CTRL BIT(0)
-+#define CCS_R_DPHY_SSC_CAPABILITY 0x162e
-+#define CCS_DPHY_SSC_CAPABILITY_SUPPORTED BIT(0)
-+#define CCS_R_CPHY_CALIBRATION_CAPABILITY 0x162f
-+#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
-+#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
-+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_1_CTRL BIT(2)
-+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_2_CTRL BIT(3)
-+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_3_CTRL BIT(4)
-+#define CCS_R_DPHY_CALIBRATION_CAPABILITY 0x1630
-+#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
-+#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
-+#define CCS_DPHY_CALIBRATION_CAPABILITY_ALTERNATE_SEQ BIT(2)
-+#define CCS_R_PHY_CTRL_CAPABILITY_2 0x1631
-+#define CCS_PHY_CTRL_CAPABILITY_2_TGR_LENGTH BIT(0)
-+#define CCS_PHY_CTRL_CAPABILITY_2_TGR_PREAMBLE_PROG_SEQ BIT(1)
-+#define CCS_PHY_CTRL_CAPABILITY_2_EXTRA_CPHY_MANUAL_TIMING BIT(2)
-+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CDPHY BIT(3)
-+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_DPHY BIT(4)
-+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CPHY BIT(5)
-+#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_DPHY BIT(6)
-+#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_CPHY BIT(7)
-+#define CCS_R_LRTE_CPHY_CAPABILITY 0x1632
-+#define CCS_LRTE_CPHY_CAPABILITY_PDQ_SHORT BIT(0)
-+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_SHORT BIT(1)
-+#define CCS_LRTE_CPHY_CAPABILITY_PDQ_LONG BIT(2)
-+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_LONG BIT(3)
-+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_NO_PDQ BIT(4)
-+#define CCS_R_LRTE_DPHY_CAPABILITY 0x1633
-+#define CCS_LRTE_DPHY_CAPABILITY_PDQ_SHORT_OPT1 BIT(0)
-+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT1 BIT(1)
-+#define CCS_LRTE_DPHY_CAPABILITY_PDQ_LONG_OPT1 BIT(2)
-+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT1 BIT(3)
-+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT2 BIT(4)
-+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT2 BIT(5)
-+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_NO_PDQ_OPT1 BIT(6)
-+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_VARIABLE_OPT2 BIT(7)
-+#define CCS_R_ALPS_CAPABILITY_DPHY 0x1634
-+#define CCS_ALPS_CAPABILITY_DPHY_LVLP_NOT_SUPPORTED 0U
-+#define CCS_ALPS_CAPABILITY_DPHY_LVLP_SUPPORTED 1U
-+#define CCS_ALPS_CAPABILITY_DPHY_CONTROLLABLE_LVLP 2U
-+#define CCS_R_ALPS_CAPABILITY_CPHY 0x1635
-+#define CCS_ALPS_CAPABILITY_CPHY_LVLP_NOT_SUPPORTED 0U
-+#define CCS_ALPS_CAPABILITY_CPHY_LVLP_SUPPORTED 1U
-+#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_LVLP 2U
-+#define CCS_ALPS_CAPABILITY_CPHY_ALP_NOT_SUPPORTED 0xc
-+#define CCS_ALPS_CAPABILITY_CPHY_ALP_SUPPORTED 0xd
-+#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_ALP 0xe
-+#define CCS_R_SCRAMBLING_CAPABILITY 0x1636
-+#define CCS_SCRAMBLING_CAPABILITY_SCRAMBLING_SUPPORTED BIT(0)
-+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_SHIFT 1U
-+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_MASK 0x6
-+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_1 0U
-+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_4 3U
-+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_SHIFT 3U
-+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_MASK 0x38
-+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_0 0U
-+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_1 1U
-+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_4 4U
-+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_PER_LANE BIT(6)
-+#define CCS_R_DPHY_MANUAL_CONSTANT 0x1637
-+#define CCS_R_CPHY_MANUAL_CONSTANT 0x1638
-+#define CCS_R_CSI2_INTERFACE_CAPABILITY_MISC 0x1639
-+#define CCS_CSI2_INTERFACE_CAPABILITY_MISC_EOTP_SHORT_PKT_OPT2 BIT(0)
-+#define CCS_R_PHY_CTRL_CAPABILITY_3 0x165c
-+#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_TIMING_NOT_MULTIPLE BIT(0)
-+#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_MIN_TIMING_VALUE_1 BIT(1)
-+#define CCS_PHY_CTRL_CAPABILITY_3_TWAKEUP_SUPPORTED BIT(2)
-+#define CCS_PHY_CTRL_CAPABILITY_3_TINIT_SUPPORTED BIT(3)
-+#define CCS_PHY_CTRL_CAPABILITY_3_THS_EXIT_SUPPORTED BIT(4)
-+#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_TIMING_NOT_MULTIPLE BIT(5)
-+#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_MIN_TIMING_VALUE_1 BIT(6)
-+#define CCS_R_DPHY_SF 0x165d
-+#define CCS_R_CPHY_SF 0x165e
-+#define CCS_CPHY_SF_TWAKEUP_SHIFT 0U
-+#define CCS_CPHY_SF_TWAKEUP_MASK 0xf
-+#define CCS_CPHY_SF_TINIT_SHIFT 4U
-+#define CCS_CPHY_SF_TINIT_MASK 0xf0
-+#define CCS_R_DPHY_LIMITS_1 0x165f
-+#define CCS_DPHY_LIMITS_1_THS_PREPARE_SHIFT 0U
-+#define CCS_DPHY_LIMITS_1_THS_PREPARE_MASK 0xf
-+#define CCS_DPHY_LIMITS_1_THS_ZERO_SHIFT 4U
-+#define CCS_DPHY_LIMITS_1_THS_ZERO_MASK 0xf0
-+#define CCS_R_DPHY_LIMITS_2 0x1660
-+#define CCS_DPHY_LIMITS_2_THS_TRAIL_SHIFT 0U
-+#define CCS_DPHY_LIMITS_2_THS_TRAIL_MASK 0xf
-+#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_SHIFT 4U
-+#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_MASK 0xf0
-+#define CCS_R_DPHY_LIMITS_3 0x1661
-+#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_SHIFT 0U
-+#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_MASK 0xf
-+#define CCS_DPHY_LIMITS_3_TCLK_ZERO_SHIFT 4U
-+#define CCS_DPHY_LIMITS_3_TCLK_ZERO_MASK 0xf0
-+#define CCS_R_DPHY_LIMITS_4 0x1662
-+#define CCS_DPHY_LIMITS_4_TCLK_POST_SHIFT 0U
-+#define CCS_DPHY_LIMITS_4_TCLK_POST_MASK 0xf
-+#define CCS_DPHY_LIMITS_4_TLPX_SHIFT 4U
-+#define CCS_DPHY_LIMITS_4_TLPX_MASK 0xf0
-+#define CCS_R_DPHY_LIMITS_5 0x1663
-+#define CCS_DPHY_LIMITS_5_THS_EXIT_SHIFT 0U
-+#define CCS_DPHY_LIMITS_5_THS_EXIT_MASK 0xf
-+#define CCS_DPHY_LIMITS_5_TWAKEUP_SHIFT 4U
-+#define CCS_DPHY_LIMITS_5_TWAKEUP_MASK 0xf0
-+#define CCS_R_DPHY_LIMITS_6 0x1664
-+#define CCS_DPHY_LIMITS_6_TINIT_SHIFT 0U
-+#define CCS_DPHY_LIMITS_6_TINIT_MASK 0xf
-+#define CCS_R_CPHY_LIMITS_1 0x1665
-+#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_SHIFT 0U
-+#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_MASK 0xf
-+#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_SHIFT 4U
-+#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_MASK 0xf0
-+#define CCS_R_CPHY_LIMITS_2 0x1666
-+#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_SHIFT 0U
-+#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_MASK 0xf
-+#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_SHIFT 4U
-+#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_MASK 0xf0
-+#define CCS_R_CPHY_LIMITS_3 0x1667
-+#define CCS_CPHY_LIMITS_3_TINIT_MAX_SHIFT 0U
-+#define CCS_CPHY_LIMITS_3_TINIT_MAX_MASK 0xf
-+#define CCS_R_MIN_FRAME_LENGTH_LINES_BIN (0x1700 | CCS_FL_16BIT)
-+#define CCS_R_MAX_FRAME_LENGTH_LINES_BIN (0x1702 | CCS_FL_16BIT)
-+#define CCS_R_MIN_LINE_LENGTH_PCK_BIN (0x1704 | CCS_FL_16BIT)
-+#define CCS_R_MAX_LINE_LENGTH_PCK_BIN (0x1706 | CCS_FL_16BIT)
-+#define CCS_R_MIN_LINE_BLANKING_PCK_BIN (0x1708 | CCS_FL_16BIT)
-+#define CCS_R_FINE_INTEGRATION_TIME_MIN_BIN (0x170a | CCS_FL_16BIT)
-+#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN (0x170c | CCS_FL_16BIT)
-+#define CCS_R_BINNING_CAPABILITY 0x1710
-+#define CCS_BINNING_CAPABILITY_UNSUPPORTED 0U
-+#define CCS_BINNING_CAPABILITY_BINNING_THEN_SUBSAMPLING 1U
-+#define CCS_BINNING_CAPABILITY_SUBSAMPLING_THEN_BINNING 2U
-+#define CCS_R_BINNING_WEIGHTING_CAPABILITY 0x1711
-+#define CCS_BINNING_WEIGHTING_CAPABILITY_AVERAGED BIT(0)
-+#define CCS_BINNING_WEIGHTING_CAPABILITY_SUMMED BIT(1)
-+#define CCS_BINNING_WEIGHTING_CAPABILITY_BAYER_CORRECTED BIT(2)
-+#define CCS_BINNING_WEIGHTING_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
-+#define CCS_R_BINNING_SUB_TYPES 0x1712
-+#define CCS_R_BINNING_SUB_TYPE(n) (0x1713 + (n))
-+#define CCS_LIM_BINNING_SUB_TYPE_MIN_N 0U
-+#define CCS_LIM_BINNING_SUB_TYPE_MAX_N 63U
-+#define CCS_BINNING_SUB_TYPE_ROW_SHIFT 0U
-+#define CCS_BINNING_SUB_TYPE_ROW_MASK 0xf
-+#define CCS_BINNING_SUB_TYPE_COLUMN_SHIFT 4U
-+#define CCS_BINNING_SUB_TYPE_COLUMN_MASK 0xf0
-+#define CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY 0x1771
-+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_AVERAGED BIT(0)
-+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_SUMMED BIT(1)
-+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_BAYER_CORRECTED BIT(2)
-+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
-+#define CCS_R_BINNING_SUB_TYPES_MONO 0x1772
-+#define CCS_R_BINNING_SUB_TYPE_MONO(n) (0x1773 + (n))
-+#define CCS_LIM_BINNING_SUB_TYPE_MONO_MIN_N 0U
-+#define CCS_LIM_BINNING_SUB_TYPE_MONO_MAX_N 63U
-+#define CCS_R_DATA_TRANSFER_IF_CAPABILITY 0x1800
-+#define CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
-+#define CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING BIT(2)
-+#define CCS_R_SHADING_CORRECTION_CAPABILITY 0x1900
-+#define CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING BIT(0)
-+#define CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION BIT(1)
-+#define CCS_R_GREEN_IMBALANCE_CAPABILITY 0x1901
-+#define CCS_GREEN_IMBALANCE_CAPABILITY_SUPPORTED BIT(0)
-+#define CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY 0x1903
-+#define CCS_R_DEFECT_CORRECTION_CAPABILITY (0x1904 | CCS_FL_16BIT)
-+#define CCS_DEFECT_CORRECTION_CAPABILITY_MAPPED_DEFECT BIT(0)
-+#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_COUPLET BIT(2)
-+#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_SINGLE BIT(5)
-+#define CCS_DEFECT_CORRECTION_CAPABILITY_COMBINED_DYNAMIC BIT(8)
-+#define CCS_R_DEFECT_CORRECTION_CAPABILITY_2 (0x1906 | CCS_FL_16BIT)
-+#define CCS_DEFECT_CORRECTION_CAPABILITY_2_DYNAMIC_TRIPLET BIT(3)
-+#define CCS_R_NF_CAPABILITY 0x1908
-+#define CCS_NF_CAPABILITY_LUMA BIT(0)
-+#define CCS_NF_CAPABILITY_CHROMA BIT(1)
-+#define CCS_NF_CAPABILITY_COMBINED BIT(2)
-+#define CCS_R_OB_READOUT_CAPABILITY 0x1980
-+#define CCS_OB_READOUT_CAPABILITY_CONTROLLABLE_READOUT BIT(0)
-+#define CCS_OB_READOUT_CAPABILITY_VISIBLE_PIXEL_READOUT BIT(1)
-+#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_VC_READOUT BIT(2)
-+#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_DT_READOUT BIT(3)
-+#define CCS_OB_READOUT_CAPABILITY_PROG_DATA_FORMAT BIT(4)
-+#define CCS_R_COLOR_FEEDBACK_CAPABILITY 0x1987
-+#define CCS_COLOR_FEEDBACK_CAPABILITY_KELVIN BIT(0)
-+#define CCS_COLOR_FEEDBACK_CAPABILITY_AWB_GAIN BIT(1)
-+#define CCS_R_CFA_PATTERN_CAPABILITY 0x1990
-+#define CCS_CFA_PATTERN_CAPABILITY_BAYER 0U
-+#define CCS_CFA_PATTERN_CAPABILITY_MONOCHROME 1U
-+#define CCS_CFA_PATTERN_CAPABILITY_4X4_QUAD_BAYER 2U
-+#define CCS_CFA_PATTERN_CAPABILITY_VENDOR_SPECIFIC 3U
-+#define CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY 0x1991
-+#define CCS_CFA_PATTERN_CONVERSION_CAPABILITY_BAYER BIT(0)
-+#define CCS_R_FLASH_MODE_CAPABILITY 0x1a02
-+#define CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
-+#define CCS_R_SA_STROBE_MODE_CAPABILITY 0x1a03
-+#define CCS_SA_STROBE_MODE_CAPABILITY_FIXED_WIDTH BIT(0)
-+#define CCS_SA_STROBE_MODE_CAPABILITY_EDGE_CTRL BIT(1)
-+#define CCS_R_RESET_MAX_DELAY 0x1a10
-+#define CCS_R_RESET_MIN_TIME 0x1a11
-+#define CCS_R_PDAF_CAPABILITY_1 0x1b80
-+#define CCS_PDAF_CAPABILITY_1_SUPPORTED BIT(0)
-+#define CCS_PDAF_CAPABILITY_1_PROCESSED_BOTTOM_EMBEDDED BIT(1)
-+#define CCS_PDAF_CAPABILITY_1_PROCESSED_INTERLEAVED BIT(2)
-+#define CCS_PDAF_CAPABILITY_1_RAW_BOTTOM_EMBEDDED BIT(3)
-+#define CCS_PDAF_CAPABILITY_1_RAW_INTERLEAVED BIT(4)
-+#define CCS_PDAF_CAPABILITY_1_VISIBLE_PDAF_CORRECTION BIT(5)
-+#define CCS_PDAF_CAPABILITY_1_VC_INTERLEAVING BIT(6)
-+#define CCS_PDAF_CAPABILITY_1_DT_INTERLEAVING BIT(7)
-+#define CCS_R_PDAF_CAPABILITY_2 0x1b81
-+#define CCS_PDAF_CAPABILITY_2_ROI BIT(0)
-+#define CCS_PDAF_CAPABILITY_2_AFTER_DIGITAL_CROP BIT(1)
-+#define CCS_PDAF_CAPABILITY_2_CTRL_RETIMED BIT(2)
-+#define CCS_R_BRACKETING_LUT_CAPABILITY_1 0x1c00
-+#define CCS_BRACKETING_LUT_CAPABILITY_1_COARSE_INTEGRATION BIT(0)
-+#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_ANALOG_GAIN BIT(1)
-+#define CCS_BRACKETING_LUT_CAPABILITY_1_FLASH BIT(4)
-+#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_DIGITAL_GAIN BIT(5)
-+#define CCS_BRACKETING_LUT_CAPABILITY_1_ALTERNATE_GLOBAL_ANALOG_GAIN BIT(6)
-+#define CCS_R_BRACKETING_LUT_CAPABILITY_2 0x1c01
-+#define CCS_BRACKETING_LUT_CAPABILITY_2_SINGLE_BRACKETING_MODE BIT(0)
-+#define CCS_BRACKETING_LUT_CAPABILITY_2_LOOPED_BRACKETING_MODE BIT(1)
-+#define CCS_R_BRACKETING_LUT_SIZE 0x1c02
-+
-+#endif /* __CCS_REGS_H__ */
---
-2.42.0
-
+++ /dev/null
-From 27daa653924573d9d8f6a7d67418e93fdb1cc47d Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 6 Feb 2020 15:06:12 +0100
-Subject: media: smiapp: Read CCS limit values
-
-From: Sakari Ailus <sakari.ailus@linux.intel.com>
-
-[ Upstream commit ca296a11156a00cc2336ba5fbcbcf2c6c41755c5 ]
-
-Read limit and capability values into a driver allocated buffer. This will
-later replace (most of) the existing SMIA limits.
-
-Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
-Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-Stable-dep-of: 724ff68e968b ("media: ccs: Correctly initialise try compose rectangle")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/media/i2c/smiapp/smiapp-core.c | 177 ++++++++++++++++++++++++-
- drivers/media/i2c/smiapp/smiapp.h | 4 +
- 2 files changed, 176 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
-index bc9c80221d2fb..4b33b9a1d52cd 100644
---- a/drivers/media/i2c/smiapp/smiapp-core.c
-+++ b/drivers/media/i2c/smiapp/smiapp-core.c
-@@ -28,6 +28,7 @@
- #include <media/v4l2-device.h>
-
- #include "ccs-limits.h"
-+#include "ccs-regs.h"
- #include "smiapp.h"
-
- #define SMIAPP_ALIGN_DIM(dim, flags) \
-@@ -102,6 +103,164 @@ static int smiapp_read_all_smia_limits(struct smiapp_sensor *sensor)
- return 0;
- }
-
-+static void ccs_assign_limit(void *ptr, unsigned int width, u32 val)
-+{
-+ switch (width) {
-+ case sizeof(u8):
-+ *(u8 *)ptr = val;
-+ break;
-+ case sizeof(u16):
-+ *(u16 *)ptr = val;
-+ break;
-+ case sizeof(u32):
-+ *(u32 *)ptr = val;
-+ break;
-+ }
-+}
-+
-+static int ccs_limit_ptr(struct smiapp_sensor *sensor, unsigned int limit,
-+ unsigned int offset, void **__ptr)
-+{
-+ const struct ccs_limit *linfo;
-+
-+ if (WARN_ON(limit >= CCS_L_LAST))
-+ return -EINVAL;
-+
-+ linfo = &ccs_limits[ccs_limit_offsets[limit].info];
-+
-+ if (WARN_ON(!sensor->ccs_limits) ||
-+ WARN_ON(offset + ccs_reg_width(linfo->reg) >
-+ ccs_limit_offsets[limit + 1].lim))
-+ return -EINVAL;
-+
-+ *__ptr = sensor->ccs_limits + ccs_limit_offsets[limit].lim + offset;
-+
-+ return 0;
-+}
-+
-+void ccs_replace_limit(struct smiapp_sensor *sensor,
-+ unsigned int limit, unsigned int offset, u32 val)
-+{
-+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
-+ const struct ccs_limit *linfo;
-+ void *ptr;
-+ int ret;
-+
-+ ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
-+ if (ret)
-+ return;
-+
-+ linfo = &ccs_limits[ccs_limit_offsets[limit].info];
-+
-+ dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" %u = %d, 0x%x\n",
-+ linfo->reg, linfo->name, offset, val, val);
-+
-+ ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val);
-+}
-+
-+static u32 ccs_get_limit(struct smiapp_sensor *sensor,
-+ unsigned int limit, unsigned int offset)
-+{
-+ void *ptr;
-+ int ret;
-+
-+ ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
-+ if (ret)
-+ return 0;
-+
-+ switch (ccs_reg_width(ccs_limits[ccs_limit_offsets[limit].info].reg)) {
-+ case sizeof(u8):
-+ return *(u8 *)ptr;
-+ case sizeof(u16):
-+ return *(u16 *)ptr;
-+ case sizeof(u32):
-+ return *(u32 *)ptr;
-+ }
-+
-+ WARN_ON(1);
-+
-+ return 0;
-+}
-+
-+#define CCS_LIM(sensor, limit) \
-+ ccs_get_limit(sensor, CCS_L_##limit, 0)
-+
-+#define CCS_LIM_AT(sensor, limit, offset) \
-+ ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset))
-+
-+static int ccs_read_all_limits(struct smiapp_sensor *sensor)
-+{
-+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
-+ void *ptr, *alloc, *end;
-+ unsigned int i, l;
-+ int ret;
-+
-+ kfree(sensor->ccs_limits);
-+ sensor->ccs_limits = NULL;
-+
-+ alloc = kzalloc(ccs_limit_offsets[CCS_L_LAST].lim, GFP_KERNEL);
-+ if (!alloc)
-+ return -ENOMEM;
-+
-+ end = alloc + ccs_limit_offsets[CCS_L_LAST].lim;
-+
-+ for (i = 0, l = 0, ptr = alloc; ccs_limits[i].size; i++) {
-+ u32 reg = ccs_limits[i].reg;
-+ unsigned int width = ccs_reg_width(reg);
-+ unsigned int j;
-+
-+ if (l == CCS_L_LAST) {
-+ dev_err(&client->dev,
-+ "internal error --- end of limit array\n");
-+ ret = -EINVAL;
-+ goto out_err;
-+ }
-+
-+ for (j = 0; j < ccs_limits[i].size / width;
-+ j++, reg += width, ptr += width) {
-+ u32 val;
-+
-+ ret = smiapp_read(sensor, reg, &val);
-+ if (ret)
-+ goto out_err;
-+
-+ if (ptr + width > end) {
-+ dev_err(&client->dev,
-+ "internal error --- no room for regs\n");
-+ ret = -EINVAL;
-+ goto out_err;
-+ }
-+
-+ ccs_assign_limit(ptr, width, val);
-+
-+ dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n",
-+ reg, ccs_limits[i].name, val, val);
-+ }
-+
-+ if (ccs_limits[i].flags & CCS_L_FL_SAME_REG)
-+ continue;
-+
-+ l++;
-+ ptr = alloc + ccs_limit_offsets[l].lim;
-+ }
-+
-+ if (l != CCS_L_LAST) {
-+ dev_err(&client->dev,
-+ "internal error --- insufficient limits\n");
-+ ret = -EINVAL;
-+ goto out_err;
-+ }
-+
-+ sensor->ccs_limits = alloc;
-+
-+ return 0;
-+
-+out_err:
-+ kfree(alloc);
-+
-+ return ret;
-+}
-+
- static int smiapp_read_frame_fmt(struct smiapp_sensor *sensor)
- {
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
-@@ -2970,10 +3129,14 @@ static int smiapp_probe(struct i2c_client *client)
- goto out_power_off;
- }
-
-+ rval = ccs_read_all_limits(sensor);
-+ if (rval)
-+ goto out_power_off;
-+
- rval = smiapp_read_frame_fmt(sensor);
- if (rval) {
- rval = -ENODEV;
-- goto out_power_off;
-+ goto out_free_ccs_limits;
- }
-
- /*
-@@ -2997,7 +3160,7 @@ static int smiapp_probe(struct i2c_client *client)
- rval = smiapp_call_quirk(sensor, limits);
- if (rval) {
- dev_err(&client->dev, "limits quirks failed\n");
-- goto out_power_off;
-+ goto out_free_ccs_limits;
- }
-
- if (SMIA_LIM(sensor, BINNING_CAPABILITY)) {
-@@ -3007,7 +3170,7 @@ static int smiapp_probe(struct i2c_client *client)
- SMIAPP_REG_U8_BINNING_SUBTYPES, &val);
- if (rval < 0) {
- rval = -ENODEV;
-- goto out_power_off;
-+ goto out_free_ccs_limits;
- }
- sensor->nbinning_subtypes = min_t(u8, val,
- SMIAPP_BINNING_SUBTYPES);
-@@ -3017,7 +3180,7 @@ static int smiapp_probe(struct i2c_client *client)
- sensor, SMIAPP_REG_U8_BINNING_TYPE_n(i), &val);
- if (rval < 0) {
- rval = -ENODEV;
-- goto out_power_off;
-+ goto out_free_ccs_limits;
- }
- sensor->binning_subtypes[i] =
- *(struct smiapp_binning_subtype *)&val;
-@@ -3033,7 +3196,7 @@ static int smiapp_probe(struct i2c_client *client)
- if (device_create_file(&client->dev, &dev_attr_ident) != 0) {
- dev_err(&client->dev, "sysfs ident entry creation failed\n");
- rval = -ENOENT;
-- goto out_power_off;
-+ goto out_free_ccs_limits;
- }
-
- if (sensor->minfo.smiapp_version &&
-@@ -3150,6 +3313,9 @@ static int smiapp_probe(struct i2c_client *client)
- out_cleanup:
- smiapp_cleanup(sensor);
-
-+out_free_ccs_limits:
-+ kfree(sensor->ccs_limits);
-+
- out_power_off:
- smiapp_power_off(&client->dev);
- mutex_destroy(&sensor->mutex);
-@@ -3176,6 +3342,7 @@ static int smiapp_remove(struct i2c_client *client)
- }
- smiapp_cleanup(sensor);
- mutex_destroy(&sensor->mutex);
-+ kfree(sensor->ccs_limits);
-
- return 0;
- }
-diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
-index 27643b36cd92b..6a20f83c3f64a 100644
---- a/drivers/media/i2c/smiapp/smiapp.h
-+++ b/drivers/media/i2c/smiapp/smiapp.h
-@@ -228,6 +228,7 @@ struct smiapp_sensor {
- struct clk *ext_clk;
- struct gpio_desc *xshutdown;
- u32 limits[SMIAPP_LIMIT_LAST];
-+ void *ccs_limits;
- u8 nbinning_subtypes;
- struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES];
- u32 mbus_frame_fmts;
-@@ -281,4 +282,7 @@ struct smiapp_sensor {
- #define to_smiapp_sensor(_sd) \
- (to_smiapp_subdev(_sd)->sensor)
-
-+void ccs_replace_limit(struct smiapp_sensor *sensor,
-+ unsigned int limit, unsigned int offset, u32 val);
-+
- #endif /* __SMIAPP_PRIV_H_ */
---
-2.42.0
-
+++ /dev/null
-From 745df51e46729efd9b14407647267117f4a312f8 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 10 Feb 2020 10:09:03 +0100
-Subject: media: smiapp: Switch to CCS limits
-
-From: Sakari Ailus <sakari.ailus@linux.intel.com>
-
-[ Upstream commit 3e158e1f1ec2aca4287bc12323c7e88d4e3b4f38 ]
-
-Use the CCS limit definitions instead of the SMIA ones. This allows
-accessing CCS capabilities where needed as well as dropping the old SMIA
-limits.
-
-Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
-Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-Stable-dep-of: 724ff68e968b ("media: ccs: Correctly initialise try compose rectangle")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/media/i2c/smiapp/Makefile | 2 +-
- drivers/media/i2c/smiapp/smiapp-core.c | 255 ++++++++++-------------
- drivers/media/i2c/smiapp/smiapp-limits.c | 118 -----------
- drivers/media/i2c/smiapp/smiapp-limits.h | 114 ----------
- drivers/media/i2c/smiapp/smiapp-quirk.c | 25 +--
- drivers/media/i2c/smiapp/smiapp-quirk.h | 3 -
- drivers/media/i2c/smiapp/smiapp.h | 10 -
- 7 files changed, 113 insertions(+), 414 deletions(-)
- delete mode 100644 drivers/media/i2c/smiapp/smiapp-limits.c
- delete mode 100644 drivers/media/i2c/smiapp/smiapp-limits.h
-
-diff --git a/drivers/media/i2c/smiapp/Makefile b/drivers/media/i2c/smiapp/Makefile
-index efb643d2acace..a7bf53dd4a637 100644
---- a/drivers/media/i2c/smiapp/Makefile
-+++ b/drivers/media/i2c/smiapp/Makefile
-@@ -1,6 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0-only
- smiapp-objs += smiapp-core.o smiapp-regs.o \
-- smiapp-quirk.o smiapp-limits.o ccs-limits.o
-+ smiapp-quirk.o ccs-limits.o
- obj-$(CONFIG_VIDEO_SMIAPP) += smiapp.o
-
- ccflags-y += -I $(srctree)/drivers/media/i2c
-diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
-index 4b33b9a1d52cd..2c1a135079654 100644
---- a/drivers/media/i2c/smiapp/smiapp-core.c
-+++ b/drivers/media/i2c/smiapp/smiapp-core.c
-@@ -64,45 +64,6 @@ static const struct smiapp_module_ident smiapp_module_idents[] = {
- *
- */
-
--static u32 smiapp_get_limit(struct smiapp_sensor *sensor,
-- unsigned int limit)
--{
-- if (WARN_ON(limit >= SMIAPP_LIMIT_LAST))
-- return 1;
--
-- return sensor->limits[limit];
--}
--
--#define SMIA_LIM(sensor, limit) \
-- smiapp_get_limit(sensor, SMIAPP_LIMIT_##limit)
--
--static int smiapp_read_all_smia_limits(struct smiapp_sensor *sensor)
--{
-- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
-- unsigned int i;
-- int rval;
--
-- for (i = 0; i < SMIAPP_LIMIT_LAST; i++) {
-- u32 val;
--
-- rval = smiapp_read(
-- sensor, smiapp_reg_limits[i].addr, &val);
-- if (rval)
-- return rval;
--
-- sensor->limits[i] = val;
--
-- dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n",
-- smiapp_reg_limits[i].addr,
-- smiapp_reg_limits[i].what, val, val);
-- }
--
-- if (SMIA_LIM(sensor, SCALER_N_MIN) == 0)
-- smiapp_replace_limit(sensor, SMIAPP_LIMIT_SCALER_N_MIN, 16);
--
-- return 0;
--}
--
- static void ccs_assign_limit(void *ptr, unsigned int width, u32 val)
- {
- switch (width) {
-@@ -253,6 +214,9 @@ static int ccs_read_all_limits(struct smiapp_sensor *sensor)
-
- sensor->ccs_limits = alloc;
-
-+ if (CCS_LIM(sensor, SCALER_N_MIN) < 16)
-+ ccs_replace_limit(sensor, CCS_L_SCALER_N_MIN, 0, 16);
-+
- return 0;
-
- out_err:
-@@ -444,35 +408,35 @@ static int smiapp_pll_try(struct smiapp_sensor *sensor,
- {
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct smiapp_pll_limits lim = {
-- .min_pre_pll_clk_div = SMIA_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
-- .max_pre_pll_clk_div = SMIA_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
-- .min_pll_ip_freq_hz = SMIA_LIM(sensor, MIN_PLL_IP_FREQ_HZ),
-- .max_pll_ip_freq_hz = SMIA_LIM(sensor, MAX_PLL_IP_FREQ_HZ),
-- .min_pll_multiplier = SMIA_LIM(sensor, MIN_PLL_MULTIPLIER),
-- .max_pll_multiplier = SMIA_LIM(sensor, MAX_PLL_MULTIPLIER),
-- .min_pll_op_freq_hz = SMIA_LIM(sensor, MIN_PLL_OP_FREQ_HZ),
-- .max_pll_op_freq_hz = SMIA_LIM(sensor, MAX_PLL_OP_FREQ_HZ),
--
-- .op.min_sys_clk_div = SMIA_LIM(sensor, MIN_OP_SYS_CLK_DIV),
-- .op.max_sys_clk_div = SMIA_LIM(sensor, MAX_OP_SYS_CLK_DIV),
-- .op.min_pix_clk_div = SMIA_LIM(sensor, MIN_OP_PIX_CLK_DIV),
-- .op.max_pix_clk_div = SMIA_LIM(sensor, MAX_OP_PIX_CLK_DIV),
-- .op.min_sys_clk_freq_hz = SMIA_LIM(sensor, MIN_OP_SYS_CLK_FREQ_HZ),
-- .op.max_sys_clk_freq_hz = SMIA_LIM(sensor, MAX_OP_SYS_CLK_FREQ_HZ),
-- .op.min_pix_clk_freq_hz = SMIA_LIM(sensor, MIN_OP_PIX_CLK_FREQ_HZ),
-- .op.max_pix_clk_freq_hz = SMIA_LIM(sensor, MAX_OP_PIX_CLK_FREQ_HZ),
--
-- .vt.min_sys_clk_div = SMIA_LIM(sensor, MIN_VT_SYS_CLK_DIV),
-- .vt.max_sys_clk_div = SMIA_LIM(sensor, MAX_VT_SYS_CLK_DIV),
-- .vt.min_pix_clk_div = SMIA_LIM(sensor, MIN_VT_PIX_CLK_DIV),
-- .vt.max_pix_clk_div = SMIA_LIM(sensor, MAX_VT_PIX_CLK_DIV),
-- .vt.min_sys_clk_freq_hz = SMIA_LIM(sensor, MIN_VT_SYS_CLK_FREQ_HZ),
-- .vt.max_sys_clk_freq_hz = SMIA_LIM(sensor, MAX_VT_SYS_CLK_FREQ_HZ),
-- .vt.min_pix_clk_freq_hz = SMIA_LIM(sensor, MIN_VT_PIX_CLK_FREQ_HZ),
-- .vt.max_pix_clk_freq_hz = SMIA_LIM(sensor, MAX_VT_PIX_CLK_FREQ_HZ),
--
-- .min_line_length_pck_bin = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN),
-- .min_line_length_pck = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK),
-+ .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
-+ .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
-+ .min_pll_ip_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ),
-+ .max_pll_ip_freq_hz = CCS_LIM(sensor, MAX_PLL_IP_CLK_FREQ_MHZ),
-+ .min_pll_multiplier = CCS_LIM(sensor, MIN_PLL_MULTIPLIER),
-+ .max_pll_multiplier = CCS_LIM(sensor, MAX_PLL_MULTIPLIER),
-+ .min_pll_op_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ),
-+ .max_pll_op_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ),
-+
-+ .op.min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV),
-+ .op.max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV),
-+ .op.min_pix_clk_div = CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV),
-+ .op.max_pix_clk_div = CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV),
-+ .op.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_OP_SYS_CLK_FREQ_MHZ),
-+ .op.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_OP_SYS_CLK_FREQ_MHZ),
-+ .op.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PIX_CLK_FREQ_MHZ),
-+ .op.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PIX_CLK_FREQ_MHZ),
-+
-+ .vt.min_sys_clk_div = CCS_LIM(sensor, MIN_VT_SYS_CLK_DIV),
-+ .vt.max_sys_clk_div = CCS_LIM(sensor, MAX_VT_SYS_CLK_DIV),
-+ .vt.min_pix_clk_div = CCS_LIM(sensor, MIN_VT_PIX_CLK_DIV),
-+ .vt.max_pix_clk_div = CCS_LIM(sensor, MAX_VT_PIX_CLK_DIV),
-+ .vt.min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_VT_SYS_CLK_FREQ_MHZ),
-+ .vt.max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_VT_SYS_CLK_FREQ_MHZ),
-+ .vt.min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_VT_PIX_CLK_FREQ_MHZ),
-+ .vt.max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_VT_PIX_CLK_FREQ_MHZ),
-+
-+ .min_line_length_pck_bin = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN),
-+ .min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK),
- };
-
- return smiapp_pll_calculate(&client->dev, &lim, pll);
-@@ -515,7 +479,7 @@ static void __smiapp_update_exposure_limits(struct smiapp_sensor *sensor)
-
- max = sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
- + sensor->vblank->val
-- - SMIA_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
-+ - CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
-
- __v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max, ctrl->step, max);
- }
-@@ -770,10 +734,10 @@ static int smiapp_init_controls(struct smiapp_sensor *sensor)
- sensor->analog_gain = v4l2_ctrl_new_std(
- &sensor->pixel_array->ctrl_handler, &smiapp_ctrl_ops,
- V4L2_CID_ANALOGUE_GAIN,
-- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MIN),
-- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MAX),
-- max(SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_STEP), 1U),
-- SMIA_LIM(sensor, ANALOGUE_GAIN_CODE_MIN));
-+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
-+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
-+ max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP), 1U),
-+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
-
- /* Exposure limits will be updated soon, use just something here. */
- sensor->exposure = v4l2_ctrl_new_std(
-@@ -1032,21 +996,21 @@ static void smiapp_update_blanking(struct smiapp_sensor *sensor)
- int min, max;
-
- if (sensor->binning_vertical > 1 || sensor->binning_horizontal > 1) {
-- min_fll = SMIA_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN);
-- max_fll = SMIA_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN);
-- min_llp = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN);
-- max_llp = SMIA_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN);
-- min_lbp = SMIA_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN);
-+ min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN);
-+ max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN);
-+ min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN);
-+ max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN);
-+ min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN);
- } else {
-- min_fll = SMIA_LIM(sensor, MIN_FRAME_LENGTH_LINES);
-- max_fll = SMIA_LIM(sensor, MAX_FRAME_LENGTH_LINES);
-- min_llp = SMIA_LIM(sensor, MIN_LINE_LENGTH_PCK);
-- max_llp = SMIA_LIM(sensor, MAX_LINE_LENGTH_PCK);
-- min_lbp = SMIA_LIM(sensor, MIN_LINE_BLANKING_PCK);
-+ min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES);
-+ max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES);
-+ min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK);
-+ max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK);
-+ min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK);
- }
-
- min = max_t(int,
-- SMIA_LIM(sensor, MIN_FRAME_BLANKING_LINES),
-+ CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES),
- min_fll -
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height);
- max = max_fll - sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height;
-@@ -1124,8 +1088,8 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
- return -ENODATA;
- }
-
-- if (SMIA_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
-- SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL) {
-+ if (CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
-+ CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING) {
- for (i = 1000; i > 0; i--) {
- if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY)
- break;
-@@ -1577,8 +1541,8 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
- */
-
- /* Digital crop */
-- if (SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
-- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
-+ if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
-+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
- rval = smiapp_write(
- sensor, SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET,
- sensor->scaler->crop[SMIAPP_PAD_SINK].left);
-@@ -1605,8 +1569,8 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
- }
-
- /* Scaling */
-- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
-- != SMIAPP_SCALING_CAPABILITY_NONE) {
-+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
-+ != CCS_SCALING_CAPABILITY_NONE) {
- rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALING_MODE,
- sensor->scaling_mode);
- if (rval < 0)
-@@ -1628,9 +1592,9 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
- if (rval < 0)
- goto out;
-
-- if ((SMIA_LIM(sensor, FLASH_MODE_CAPABILITY) &
-- (SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE |
-- SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE)) &&
-+ if (CCS_LIM(sensor, FLASH_MODE_CAPABILITY) &
-+ (CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE |
-+ SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) &&
- sensor->hwcfg->strobe_setup != NULL &&
- sensor->hwcfg->strobe_setup->trigger != 0) {
- rval = smiapp_setup_flash_strobe(sensor);
-@@ -1876,7 +1840,7 @@ static void smiapp_propagate(struct v4l2_subdev *subdev,
- if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
- if (ssd == sensor->scaler) {
- sensor->scale_m =
-- SMIA_LIM(sensor, SCALER_N_MIN);
-+ CCS_LIM(sensor, SCALER_N_MIN);
- sensor->scaling_mode =
- SMIAPP_SCALING_MODE_NONE;
- } else if (ssd == sensor->binner) {
-@@ -1988,12 +1952,12 @@ static int smiapp_set_format(struct v4l2_subdev *subdev,
-
- fmt->format.width =
- clamp(fmt->format.width,
-- SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE),
-- SMIA_LIM(sensor, MAX_X_OUTPUT_SIZE));
-+ CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
-+ CCS_LIM(sensor, MAX_X_OUTPUT_SIZE));
- fmt->format.height =
- clamp(fmt->format.height,
-- SMIA_LIM(sensor, MIN_Y_OUTPUT_SIZE),
-- SMIA_LIM(sensor, MAX_Y_OUTPUT_SIZE));
-+ CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
-+ CCS_LIM(sensor, MAX_Y_OUTPUT_SIZE));
-
- smiapp_get_crop_compose(subdev, cfg, crops, NULL, fmt->which);
-
-@@ -2046,7 +2010,7 @@ static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w,
- val -= abs(w - ask_w);
- val -= abs(h - ask_h);
-
-- if (w < SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE))
-+ if (w < CCS_LIM(sensor, MIN_X_OUTPUT_SIZE))
- val -= SCALING_GOODNESS_EXTREME;
-
- dev_dbg(&client->dev, "w %d ask_w %d h %d ask_h %d goodness %d\n",
-@@ -2112,7 +2076,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
- struct i2c_client *client = v4l2_get_subdevdata(subdev);
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- u32 min, max, a, b, max_m;
-- u32 scale_m = SMIA_LIM(sensor, SCALER_N_MIN);
-+ u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN);
- int mode = SMIAPP_SCALING_MODE_HORIZONTAL;
- u32 try[4];
- u32 ntry = 0;
-@@ -2125,19 +2089,19 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
- crops[SMIAPP_PAD_SINK]->height);
-
- a = crops[SMIAPP_PAD_SINK]->width
-- * SMIA_LIM(sensor, SCALER_N_MIN) / sel->r.width;
-+ * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.width;
- b = crops[SMIAPP_PAD_SINK]->height
-- * SMIA_LIM(sensor, SCALER_N_MIN) / sel->r.height;
-+ * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.height;
- max_m = crops[SMIAPP_PAD_SINK]->width
-- * SMIA_LIM(sensor, SCALER_N_MIN)
-- / SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE);
-+ * CCS_LIM(sensor, SCALER_N_MIN)
-+ / CCS_LIM(sensor, MIN_X_OUTPUT_SIZE);
-
-- a = clamp(a, SMIA_LIM(sensor, SCALER_M_MIN),
-- SMIA_LIM(sensor, SCALER_M_MAX));
-- b = clamp(b, SMIA_LIM(sensor, SCALER_M_MIN),
-- SMIA_LIM(sensor, SCALER_M_MAX));
-- max_m = clamp(max_m, SMIA_LIM(sensor, SCALER_M_MIN),
-- SMIA_LIM(sensor, SCALER_M_MAX));
-+ a = clamp(a, CCS_LIM(sensor, SCALER_M_MIN),
-+ CCS_LIM(sensor, SCALER_M_MAX));
-+ b = clamp(b, CCS_LIM(sensor, SCALER_M_MIN),
-+ CCS_LIM(sensor, SCALER_M_MAX));
-+ max_m = clamp(max_m, CCS_LIM(sensor, SCALER_M_MIN),
-+ CCS_LIM(sensor, SCALER_M_MAX));
-
- dev_dbg(&client->dev, "scaling: a %d b %d max_m %d\n", a, b, max_m);
-
-@@ -2163,8 +2127,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
- int this = scaling_goodness(
- subdev,
- crops[SMIAPP_PAD_SINK]->width
-- / try[i]
-- * SMIA_LIM(sensor, SCALER_N_MIN),
-+ / try[i] * CCS_LIM(sensor, SCALER_N_MIN),
- sel->r.width,
- crops[SMIAPP_PAD_SINK]->height,
- sel->r.height,
-@@ -2178,18 +2141,18 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
- best = this;
- }
-
-- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
-- == SMIAPP_SCALING_CAPABILITY_HORIZONTAL)
-+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
-+ == CCS_SCALING_CAPABILITY_HORIZONTAL)
- continue;
-
- this = scaling_goodness(
- subdev, crops[SMIAPP_PAD_SINK]->width
- / try[i]
-- * SMIA_LIM(sensor, SCALER_N_MIN),
-+ * CCS_LIM(sensor, SCALER_N_MIN),
- sel->r.width,
- crops[SMIAPP_PAD_SINK]->height
- / try[i]
-- * SMIA_LIM(sensor, SCALER_N_MIN),
-+ * CCS_LIM(sensor, SCALER_N_MIN),
- sel->r.height,
- sel->flags);
-
-@@ -2203,12 +2166,12 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
- sel->r.width =
- (crops[SMIAPP_PAD_SINK]->width
- / scale_m
-- * SMIA_LIM(sensor, SCALER_N_MIN)) & ~1;
-+ * CCS_LIM(sensor, SCALER_N_MIN)) & ~1;
- if (mode == SMIAPP_SCALING_MODE_BOTH)
- sel->r.height =
- (crops[SMIAPP_PAD_SINK]->height
- / scale_m
-- * SMIA_LIM(sensor, SCALER_N_MIN))
-+ * CCS_LIM(sensor, SCALER_N_MIN))
- & ~1;
- else
- sel->r.height = crops[SMIAPP_PAD_SINK]->height;
-@@ -2262,10 +2225,9 @@ static int __smiapp_sel_supported(struct v4l2_subdev *subdev,
- if (ssd == sensor->src
- && sel->pad == SMIAPP_PAD_SRC)
- return 0;
-- if (ssd == sensor->scaler
-- && sel->pad == SMIAPP_PAD_SINK
-- && SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
-- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
-+ if (ssd == sensor->scaler && sel->pad == SMIAPP_PAD_SINK &&
-+ CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
-+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
- return 0;
- return -EINVAL;
- case V4L2_SEL_TGT_NATIVE_SIZE:
-@@ -2279,9 +2241,8 @@ static int __smiapp_sel_supported(struct v4l2_subdev *subdev,
- return -EINVAL;
- if (ssd == sensor->binner)
- return 0;
-- if (ssd == sensor->scaler
-- && SMIA_LIM(sensor, SCALING_CAPABILITY)
-- != SMIAPP_SCALING_CAPABILITY_NONE)
-+ if (ssd == sensor->scaler && CCS_LIM(sensor, SCALING_CAPABILITY)
-+ != CCS_SCALING_CAPABILITY_NONE)
- return 0;
- fallthrough;
- default:
-@@ -2345,8 +2306,8 @@ static void smiapp_get_native_size(struct smiapp_subdev *ssd,
- {
- r->top = 0;
- r->left = 0;
-- r->width = SMIA_LIM(ssd->sensor, X_ADDR_MAX) + 1;
-- r->height = SMIA_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
-+ r->width = CCS_LIM(ssd->sensor, X_ADDR_MAX) + 1;
-+ r->height = CCS_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
- }
-
- static int __smiapp_get_selection(struct v4l2_subdev *subdev,
-@@ -2431,10 +2392,10 @@ static int smiapp_set_selection(struct v4l2_subdev *subdev,
- sel->r.height = SMIAPP_ALIGN_DIM(sel->r.height, sel->flags);
-
- sel->r.width = max_t(unsigned int,
-- SMIA_LIM(sensor, MIN_X_OUTPUT_SIZE),
-+ CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
- sel->r.width);
- sel->r.height = max_t(unsigned int,
-- SMIA_LIM(sensor, MIN_Y_OUTPUT_SIZE),
-+ CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
- sel->r.height);
-
- switch (sel->target) {
-@@ -3123,12 +3084,6 @@ static int smiapp_probe(struct i2c_client *client)
- goto out_power_off;
- }
-
-- rval = smiapp_read_all_smia_limits(sensor);
-- if (rval) {
-- rval = -ENODEV;
-- goto out_power_off;
-- }
--
- rval = ccs_read_all_limits(sensor);
- if (rval)
- goto out_power_off;
-@@ -3163,7 +3118,7 @@ static int smiapp_probe(struct i2c_client *client)
- goto out_free_ccs_limits;
- }
-
-- if (SMIA_LIM(sensor, BINNING_CAPABILITY)) {
-+ if (CCS_LIM(sensor, BINNING_CAPABILITY)) {
- u32 val;
-
- rval = smiapp_read(sensor,
-@@ -3200,8 +3155,8 @@ static int smiapp_probe(struct i2c_client *client)
- }
-
- if (sensor->minfo.smiapp_version &&
-- SMIA_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
-- SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) {
-+ CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
-+ CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) {
- if (device_create_file(&client->dev, &dev_attr_nvm) != 0) {
- dev_err(&client->dev, "sysfs nvm entry failed\n");
- rval = -EBUSY;
-@@ -3210,22 +3165,22 @@ static int smiapp_probe(struct i2c_client *client)
- }
-
- /* We consider this as profile 0 sensor if any of these are zero. */
-- if (!SMIA_LIM(sensor, MIN_OP_SYS_CLK_DIV) ||
-- !SMIA_LIM(sensor, MAX_OP_SYS_CLK_DIV) ||
-- !SMIA_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
-- !SMIA_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
-+ if (!CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV) ||
-+ !CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV) ||
-+ !CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
-+ !CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_0;
-- } else if (SMIA_LIM(sensor, SCALING_CAPABILITY)
-- != SMIAPP_SCALING_CAPABILITY_NONE) {
-- if (SMIA_LIM(sensor, SCALING_CAPABILITY)
-- == SMIAPP_SCALING_CAPABILITY_HORIZONTAL)
-+ } else if (CCS_LIM(sensor, SCALING_CAPABILITY)
-+ != CCS_SCALING_CAPABILITY_NONE) {
-+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
-+ == CCS_SCALING_CAPABILITY_HORIZONTAL)
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_1;
- else
- sensor->minfo.smiapp_profile = SMIAPP_PROFILE_2;
- sensor->scaler = &sensor->ssds[sensor->ssds_used];
- sensor->ssds_used++;
-- } else if (SMIA_LIM(sensor, DIGITAL_CROP_CAPABILITY)
-- == SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
-+ } else if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
-+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
- sensor->scaler = &sensor->ssds[sensor->ssds_used];
- sensor->ssds_used++;
- }
-@@ -3234,13 +3189,13 @@ static int smiapp_probe(struct i2c_client *client)
- sensor->pixel_array = &sensor->ssds[sensor->ssds_used];
- sensor->ssds_used++;
-
-- sensor->scale_m = SMIA_LIM(sensor, SCALER_N_MIN);
-+ sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
-
- /* prepare PLL configuration input values */
- sensor->pll.bus_type = SMIAPP_PLL_BUS_TYPE_CSI2;
- sensor->pll.csi2.lanes = sensor->hwcfg->lanes;
- sensor->pll.ext_clk_freq_hz = sensor->hwcfg->ext_clk;
-- sensor->pll.scale_n = SMIA_LIM(sensor, SCALER_N_MIN);
-+ sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
- /* Profile 0 sensors have no separate OP clock branch. */
- if (sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
- sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
-diff --git a/drivers/media/i2c/smiapp/smiapp-limits.c b/drivers/media/i2c/smiapp/smiapp-limits.c
-deleted file mode 100644
-index de5ee52967138..0000000000000
---- a/drivers/media/i2c/smiapp/smiapp-limits.c
-+++ /dev/null
-@@ -1,118 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0-only
--/*
-- * drivers/media/i2c/smiapp/smiapp-limits.c
-- *
-- * Generic driver for SMIA/SMIA++ compliant camera modules
-- *
-- * Copyright (C) 2011--2012 Nokia Corporation
-- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
-- */
--
--#include "smiapp.h"
--
--struct smiapp_reg_limits smiapp_reg_limits[] = {
-- { SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY, "analogue_gain_capability" }, /* 0 */
-- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN, "analogue_gain_code_min" },
-- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX, "analogue_gain_code_max" },
-- { SMIAPP_REG_U8_THS_ZERO_MIN, "ths_zero_min" },
-- { SMIAPP_REG_U8_TCLK_TRAIL_MIN, "tclk_trail_min" },
-- { SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY, "integration_time_capability" }, /* 5 */
-- { SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN, "coarse_integration_time_min" },
-- { SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN, "coarse_integration_time_max_margin" },
-- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN, "fine_integration_time_min" },
-- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN, "fine_integration_time_max_margin" },
-- { SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY, "digital_gain_capability" }, /* 10 */
-- { SMIAPP_REG_U16_DIGITAL_GAIN_MIN, "digital_gain_min" },
-- { SMIAPP_REG_U16_DIGITAL_GAIN_MAX, "digital_gain_max" },
-- { SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ, "min_ext_clk_freq_hz" },
-- { SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ, "max_ext_clk_freq_hz" },
-- { SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV, "min_pre_pll_clk_div" }, /* 15 */
-- { SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV, "max_pre_pll_clk_div" },
-- { SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ, "min_pll_ip_freq_hz" },
-- { SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ, "max_pll_ip_freq_hz" },
-- { SMIAPP_REG_U16_MIN_PLL_MULTIPLIER, "min_pll_multiplier" },
-- { SMIAPP_REG_U16_MAX_PLL_MULTIPLIER, "max_pll_multiplier" }, /* 20 */
-- { SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ, "min_pll_op_freq_hz" },
-- { SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ, "max_pll_op_freq_hz" },
-- { SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV, "min_vt_sys_clk_div" },
-- { SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV, "max_vt_sys_clk_div" },
-- { SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ, "min_vt_sys_clk_freq_hz" }, /* 25 */
-- { SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ, "max_vt_sys_clk_freq_hz" },
-- { SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ, "min_vt_pix_clk_freq_hz" },
-- { SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ, "max_vt_pix_clk_freq_hz" },
-- { SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV, "min_vt_pix_clk_div" },
-- { SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV, "max_vt_pix_clk_div" }, /* 30 */
-- { SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES, "min_frame_length_lines" },
-- { SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES, "max_frame_length_lines" },
-- { SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK, "min_line_length_pck" },
-- { SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK, "max_line_length_pck" },
-- { SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK, "min_line_blanking_pck" }, /* 35 */
-- { SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES, "min_frame_blanking_lines" },
-- { SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE, "min_line_length_pck_step_size" },
-- { SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV, "min_op_sys_clk_div" },
-- { SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV, "max_op_sys_clk_div" },
-- { SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ, "min_op_sys_clk_freq_hz" }, /* 40 */
-- { SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ, "max_op_sys_clk_freq_hz" },
-- { SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV, "min_op_pix_clk_div" },
-- { SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV, "max_op_pix_clk_div" },
-- { SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ, "min_op_pix_clk_freq_hz" },
-- { SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ, "max_op_pix_clk_freq_hz" }, /* 45 */
-- { SMIAPP_REG_U16_X_ADDR_MIN, "x_addr_min" },
-- { SMIAPP_REG_U16_Y_ADDR_MIN, "y_addr_min" },
-- { SMIAPP_REG_U16_X_ADDR_MAX, "x_addr_max" },
-- { SMIAPP_REG_U16_Y_ADDR_MAX, "y_addr_max" },
-- { SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE, "min_x_output_size" }, /* 50 */
-- { SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE, "min_y_output_size" },
-- { SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE, "max_x_output_size" },
-- { SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE, "max_y_output_size" },
-- { SMIAPP_REG_U16_MIN_EVEN_INC, "min_even_inc" },
-- { SMIAPP_REG_U16_MAX_EVEN_INC, "max_even_inc" }, /* 55 */
-- { SMIAPP_REG_U16_MIN_ODD_INC, "min_odd_inc" },
-- { SMIAPP_REG_U16_MAX_ODD_INC, "max_odd_inc" },
-- { SMIAPP_REG_U16_SCALING_CAPABILITY, "scaling_capability" },
-- { SMIAPP_REG_U16_SCALER_M_MIN, "scaler_m_min" },
-- { SMIAPP_REG_U16_SCALER_M_MAX, "scaler_m_max" }, /* 60 */
-- { SMIAPP_REG_U16_SCALER_N_MIN, "scaler_n_min" },
-- { SMIAPP_REG_U16_SCALER_N_MAX, "scaler_n_max" },
-- { SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY, "spatial_sampling_capability" },
-- { SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY, "digital_crop_capability" },
-- { SMIAPP_REG_U16_COMPRESSION_CAPABILITY, "compression_capability" }, /* 65 */
-- { SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY, "fifo_support_capability" },
-- { SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY, "dphy_ctrl_capability" },
-- { SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY, "csi_lane_mode_capability" },
-- { SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY, "csi_signalling_mode_capability" },
-- { SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY, "fast_standby_capability" }, /* 70 */
-- { SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY, "cci_address_control_capability" },
-- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS, "max_per_lane_bitrate_1_lane_mode_mbps" },
-- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS, "max_per_lane_bitrate_2_lane_mode_mbps" },
-- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS, "max_per_lane_bitrate_3_lane_mode_mbps" },
-- { SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS, "max_per_lane_bitrate_4_lane_mode_mbps" }, /* 75 */
-- { SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY, "temp_sensor_capability" },
-- { SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN, "min_frame_length_lines_bin" },
-- { SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN, "max_frame_length_lines_bin" },
-- { SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN, "min_line_length_pck_bin" },
-- { SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN, "max_line_length_pck_bin" }, /* 80 */
-- { SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN, "min_line_blanking_pck_bin" },
-- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN, "fine_integration_time_min_bin" },
-- { SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, "fine_integration_time_max_margin_bin" },
-- { SMIAPP_REG_U8_BINNING_CAPABILITY, "binning_capability" },
-- { SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY, "binning_weighting_capability" }, /* 85 */
-- { SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY, "data_transfer_if_capability" },
-- { SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY, "shading_correction_capability" },
-- { SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY, "green_imbalance_capability" },
-- { SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY, "black_level_capability" },
-- { SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY, "module_specific_correction_capability" }, /* 90 */
-- { SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY, "defect_correction_capability" },
-- { SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2, "defect_correction_capability_2" },
-- { SMIAPP_REG_U8_EDOF_CAPABILITY, "edof_capability" },
-- { SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY, "colour_feedback_capability" },
-- { SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY, "estimation_mode_capability" }, /* 95 */
-- { SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY, "estimation_zone_capability" },
-- { SMIAPP_REG_U16_CAPABILITY_TRDY_MIN, "capability_trdy_min" },
-- { SMIAPP_REG_U8_FLASH_MODE_CAPABILITY, "flash_mode_capability" },
-- { SMIAPP_REG_U8_ACTUATOR_CAPABILITY, "actuator_capability" },
-- { SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1, "bracketing_lut_capability_1" }, /* 100 */
-- { SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2, "bracketing_lut_capability_2" },
-- { SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP, "analogue_gain_code_step" },
-- { 0, NULL },
--};
-diff --git a/drivers/media/i2c/smiapp/smiapp-limits.h b/drivers/media/i2c/smiapp/smiapp-limits.h
-deleted file mode 100644
-index dbac0b4975f96..0000000000000
---- a/drivers/media/i2c/smiapp/smiapp-limits.h
-+++ /dev/null
-@@ -1,114 +0,0 @@
--/* SPDX-License-Identifier: GPL-2.0-only */
--/*
-- * drivers/media/i2c/smiapp/smiapp-limits.h
-- *
-- * Generic driver for SMIA/SMIA++ compliant camera modules
-- *
-- * Copyright (C) 2011--2012 Nokia Corporation
-- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
-- */
--
--#define SMIAPP_LIMIT_ANALOGUE_GAIN_CAPABILITY 0
--#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN 1
--#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX 2
--#define SMIAPP_LIMIT_THS_ZERO_MIN 3
--#define SMIAPP_LIMIT_TCLK_TRAIL_MIN 4
--#define SMIAPP_LIMIT_INTEGRATION_TIME_CAPABILITY 5
--#define SMIAPP_LIMIT_COARSE_INTEGRATION_TIME_MIN 6
--#define SMIAPP_LIMIT_COARSE_INTEGRATION_TIME_MAX_MARGIN 7
--#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MIN 8
--#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MAX_MARGIN 9
--#define SMIAPP_LIMIT_DIGITAL_GAIN_CAPABILITY 10
--#define SMIAPP_LIMIT_DIGITAL_GAIN_MIN 11
--#define SMIAPP_LIMIT_DIGITAL_GAIN_MAX 12
--#define SMIAPP_LIMIT_MIN_EXT_CLK_FREQ_HZ 13
--#define SMIAPP_LIMIT_MAX_EXT_CLK_FREQ_HZ 14
--#define SMIAPP_LIMIT_MIN_PRE_PLL_CLK_DIV 15
--#define SMIAPP_LIMIT_MAX_PRE_PLL_CLK_DIV 16
--#define SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ 17
--#define SMIAPP_LIMIT_MAX_PLL_IP_FREQ_HZ 18
--#define SMIAPP_LIMIT_MIN_PLL_MULTIPLIER 19
--#define SMIAPP_LIMIT_MAX_PLL_MULTIPLIER 20
--#define SMIAPP_LIMIT_MIN_PLL_OP_FREQ_HZ 21
--#define SMIAPP_LIMIT_MAX_PLL_OP_FREQ_HZ 22
--#define SMIAPP_LIMIT_MIN_VT_SYS_CLK_DIV 23
--#define SMIAPP_LIMIT_MAX_VT_SYS_CLK_DIV 24
--#define SMIAPP_LIMIT_MIN_VT_SYS_CLK_FREQ_HZ 25
--#define SMIAPP_LIMIT_MAX_VT_SYS_CLK_FREQ_HZ 26
--#define SMIAPP_LIMIT_MIN_VT_PIX_CLK_FREQ_HZ 27
--#define SMIAPP_LIMIT_MAX_VT_PIX_CLK_FREQ_HZ 28
--#define SMIAPP_LIMIT_MIN_VT_PIX_CLK_DIV 29
--#define SMIAPP_LIMIT_MAX_VT_PIX_CLK_DIV 30
--#define SMIAPP_LIMIT_MIN_FRAME_LENGTH_LINES 31
--#define SMIAPP_LIMIT_MAX_FRAME_LENGTH_LINES 32
--#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK 33
--#define SMIAPP_LIMIT_MAX_LINE_LENGTH_PCK 34
--#define SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK 35
--#define SMIAPP_LIMIT_MIN_FRAME_BLANKING_LINES 36
--#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK_STEP_SIZE 37
--#define SMIAPP_LIMIT_MIN_OP_SYS_CLK_DIV 38
--#define SMIAPP_LIMIT_MAX_OP_SYS_CLK_DIV 39
--#define SMIAPP_LIMIT_MIN_OP_SYS_CLK_FREQ_HZ 40
--#define SMIAPP_LIMIT_MAX_OP_SYS_CLK_FREQ_HZ 41
--#define SMIAPP_LIMIT_MIN_OP_PIX_CLK_DIV 42
--#define SMIAPP_LIMIT_MAX_OP_PIX_CLK_DIV 43
--#define SMIAPP_LIMIT_MIN_OP_PIX_CLK_FREQ_HZ 44
--#define SMIAPP_LIMIT_MAX_OP_PIX_CLK_FREQ_HZ 45
--#define SMIAPP_LIMIT_X_ADDR_MIN 46
--#define SMIAPP_LIMIT_Y_ADDR_MIN 47
--#define SMIAPP_LIMIT_X_ADDR_MAX 48
--#define SMIAPP_LIMIT_Y_ADDR_MAX 49
--#define SMIAPP_LIMIT_MIN_X_OUTPUT_SIZE 50
--#define SMIAPP_LIMIT_MIN_Y_OUTPUT_SIZE 51
--#define SMIAPP_LIMIT_MAX_X_OUTPUT_SIZE 52
--#define SMIAPP_LIMIT_MAX_Y_OUTPUT_SIZE 53
--#define SMIAPP_LIMIT_MIN_EVEN_INC 54
--#define SMIAPP_LIMIT_MAX_EVEN_INC 55
--#define SMIAPP_LIMIT_MIN_ODD_INC 56
--#define SMIAPP_LIMIT_MAX_ODD_INC 57
--#define SMIAPP_LIMIT_SCALING_CAPABILITY 58
--#define SMIAPP_LIMIT_SCALER_M_MIN 59
--#define SMIAPP_LIMIT_SCALER_M_MAX 60
--#define SMIAPP_LIMIT_SCALER_N_MIN 61
--#define SMIAPP_LIMIT_SCALER_N_MAX 62
--#define SMIAPP_LIMIT_SPATIAL_SAMPLING_CAPABILITY 63
--#define SMIAPP_LIMIT_DIGITAL_CROP_CAPABILITY 64
--#define SMIAPP_LIMIT_COMPRESSION_CAPABILITY 65
--#define SMIAPP_LIMIT_FIFO_SUPPORT_CAPABILITY 66
--#define SMIAPP_LIMIT_DPHY_CTRL_CAPABILITY 67
--#define SMIAPP_LIMIT_CSI_LANE_MODE_CAPABILITY 68
--#define SMIAPP_LIMIT_CSI_SIGNALLING_MODE_CAPABILITY 69
--#define SMIAPP_LIMIT_FAST_STANDBY_CAPABILITY 70
--#define SMIAPP_LIMIT_CCI_ADDRESS_CONTROL_CAPABILITY 71
--#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS 72
--#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS 73
--#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS 74
--#define SMIAPP_LIMIT_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS 75
--#define SMIAPP_LIMIT_TEMP_SENSOR_CAPABILITY 76
--#define SMIAPP_LIMIT_MIN_FRAME_LENGTH_LINES_BIN 77
--#define SMIAPP_LIMIT_MAX_FRAME_LENGTH_LINES_BIN 78
--#define SMIAPP_LIMIT_MIN_LINE_LENGTH_PCK_BIN 79
--#define SMIAPP_LIMIT_MAX_LINE_LENGTH_PCK_BIN 80
--#define SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN 81
--#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MIN_BIN 82
--#define SMIAPP_LIMIT_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN 83
--#define SMIAPP_LIMIT_BINNING_CAPABILITY 84
--#define SMIAPP_LIMIT_BINNING_WEIGHTING_CAPABILITY 85
--#define SMIAPP_LIMIT_DATA_TRANSFER_IF_CAPABILITY 86
--#define SMIAPP_LIMIT_SHADING_CORRECTION_CAPABILITY 87
--#define SMIAPP_LIMIT_GREEN_IMBALANCE_CAPABILITY 88
--#define SMIAPP_LIMIT_BLACK_LEVEL_CAPABILITY 89
--#define SMIAPP_LIMIT_MODULE_SPECIFIC_CORRECTION_CAPABILITY 90
--#define SMIAPP_LIMIT_DEFECT_CORRECTION_CAPABILITY 91
--#define SMIAPP_LIMIT_DEFECT_CORRECTION_CAPABILITY_2 92
--#define SMIAPP_LIMIT_EDOF_CAPABILITY 93
--#define SMIAPP_LIMIT_COLOUR_FEEDBACK_CAPABILITY 94
--#define SMIAPP_LIMIT_ESTIMATION_MODE_CAPABILITY 95
--#define SMIAPP_LIMIT_ESTIMATION_ZONE_CAPABILITY 96
--#define SMIAPP_LIMIT_CAPABILITY_TRDY_MIN 97
--#define SMIAPP_LIMIT_FLASH_MODE_CAPABILITY 98
--#define SMIAPP_LIMIT_ACTUATOR_CAPABILITY 99
--#define SMIAPP_LIMIT_BRACKETING_LUT_CAPABILITY_1 100
--#define SMIAPP_LIMIT_BRACKETING_LUT_CAPABILITY_2 101
--#define SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_STEP 102
--#define SMIAPP_LIMIT_LAST 103
-diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.c b/drivers/media/i2c/smiapp/smiapp-quirk.c
-index ab96d6067fc35..3251026e030a7 100644
---- a/drivers/media/i2c/smiapp/smiapp-quirk.c
-+++ b/drivers/media/i2c/smiapp/smiapp-quirk.c
-@@ -10,6 +10,8 @@
-
- #include <linux/delay.h>
-
-+#include "ccs-limits.h"
-+
- #include "smiapp.h"
-
- static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val)
-@@ -36,17 +38,6 @@ static int smiapp_write_8s(struct smiapp_sensor *sensor,
- return 0;
- }
-
--void smiapp_replace_limit(struct smiapp_sensor *sensor,
-- u32 limit, u32 val)
--{
-- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
--
-- dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" = %d, 0x%x\n",
-- smiapp_reg_limits[limit].addr,
-- smiapp_reg_limits[limit].what, val, val);
-- sensor->limits[limit] = val;
--}
--
- static int jt8ew9_limits(struct smiapp_sensor *sensor)
- {
- if (sensor->minfo.revision_number_major < 0x03)
-@@ -54,9 +45,8 @@ static int jt8ew9_limits(struct smiapp_sensor *sensor)
-
- /* Below 24 gain doesn't have effect at all, */
- /* but ~59 is needed for full dynamic range */
-- smiapp_replace_limit(sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN, 59);
-- smiapp_replace_limit(
-- sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX, 6000);
-+ ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MIN, 0, 59);
-+ ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MAX, 0, 6000);
-
- return 0;
- }
-@@ -126,9 +116,8 @@ const struct smiapp_quirk smiapp_imx125es_quirk = {
-
- static int jt8ev1_limits(struct smiapp_sensor *sensor)
- {
-- smiapp_replace_limit(sensor, SMIAPP_LIMIT_X_ADDR_MAX, 4271);
-- smiapp_replace_limit(sensor,
-- SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN, 184);
-+ ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271);
-+ ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184);
-
- return 0;
- }
-@@ -221,7 +210,7 @@ const struct smiapp_quirk smiapp_jt8ev1_quirk = {
-
- static int tcm8500md_limits(struct smiapp_sensor *sensor)
- {
-- smiapp_replace_limit(sensor, SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ, 2700000);
-+ ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000);
-
- return 0;
- }
-diff --git a/drivers/media/i2c/smiapp/smiapp-quirk.h b/drivers/media/i2c/smiapp/smiapp-quirk.h
-index 17505be60c1d4..8a479f17cd19b 100644
---- a/drivers/media/i2c/smiapp/smiapp-quirk.h
-+++ b/drivers/media/i2c/smiapp/smiapp-quirk.h
-@@ -55,9 +55,6 @@ struct smiapp_reg_8 {
- u8 val;
- };
-
--void smiapp_replace_limit(struct smiapp_sensor *sensor,
-- u32 limit, u32 val);
--
- #define SMIAPP_MK_QUIRK_REG_8(_reg, _val) \
- { \
- .reg = (u16)_reg, \
-diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
-index 6a20f83c3f64a..76c29b7723fb1 100644
---- a/drivers/media/i2c/smiapp/smiapp.h
-+++ b/drivers/media/i2c/smiapp/smiapp.h
-@@ -84,8 +84,6 @@ struct smiapp_hwconfig {
- struct smiapp_flash_strobe_parms *strobe_setup;
- };
-
--#include "smiapp-limits.h"
--
- struct smiapp_quirk;
-
- #define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0)
-@@ -167,13 +165,6 @@ struct smiapp_module_info {
- .flags = 0, \
- .name = _name, }
-
--struct smiapp_reg_limits {
-- u32 addr;
-- char *what;
--};
--
--extern struct smiapp_reg_limits smiapp_reg_limits[];
--
- struct smiapp_csi_data_format {
- u32 code;
- u8 width;
-@@ -227,7 +218,6 @@ struct smiapp_sensor {
- struct regulator *vana;
- struct clk *ext_clk;
- struct gpio_desc *xshutdown;
-- u32 limits[SMIAPP_LIMIT_LAST];
- void *ccs_limits;
- u8 nbinning_subtypes;
- struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES];
---
-2.42.0
-
+++ /dev/null
-From cdd031141f715e84c9bd3954c32dc484b7da30a1 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 3 Feb 2020 12:38:42 +0100
-Subject: media: smiapp: Use CCS register flags
-
-From: Sakari Ailus <sakari.ailus@linux.intel.com>
-
-[ Upstream commit 82731a194fc155eb734941bb1f777caea4077ffa ]
-
-Use the CCS register flags instead of the old smia flags. The
-new flags include the register width information that was separate from
-the register flags previously.
-
-Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
-Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-Stable-dep-of: 724ff68e968b ("media: ccs: Correctly initialise try compose rectangle")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/media/i2c/smiapp/smiapp-reg-defs.h | 8 ++++----
- drivers/media/i2c/smiapp/smiapp-regs.c | 20 +++++++++++++-------
- drivers/media/i2c/smiapp/smiapp-regs.h | 13 ++++---------
- 3 files changed, 21 insertions(+), 20 deletions(-)
-
-diff --git a/drivers/media/i2c/smiapp/smiapp-reg-defs.h b/drivers/media/i2c/smiapp/smiapp-reg-defs.h
-index 865488befc09c..ec574007908bc 100644
---- a/drivers/media/i2c/smiapp/smiapp-reg-defs.h
-+++ b/drivers/media/i2c/smiapp/smiapp-reg-defs.h
-@@ -7,11 +7,11 @@
- * Copyright (C) 2011--2012 Nokia Corporation
- * Contact: Sakari Ailus <sakari.ailus@iki.fi>
- */
--#define SMIAPP_REG_MK_U8(r) ((SMIAPP_REG_8BIT << 16) | (r))
--#define SMIAPP_REG_MK_U16(r) ((SMIAPP_REG_16BIT << 16) | (r))
--#define SMIAPP_REG_MK_U32(r) ((SMIAPP_REG_32BIT << 16) | (r))
-+#define SMIAPP_REG_MK_U8(r) (r)
-+#define SMIAPP_REG_MK_U16(r) (CCS_FL_16BIT | (r))
-+#define SMIAPP_REG_MK_U32(r) (CCS_FL_32BIT | (r))
-
--#define SMIAPP_REG_MK_F32(r) (SMIAPP_REG_FLAG_FLOAT | (SMIAPP_REG_32BIT << 16) | (r))
-+#define SMIAPP_REG_MK_F32(r) (CCS_FL_FLOAT_IREAL | CCS_FL_32BIT | (r))
-
- #define SMIAPP_REG_U16_MODEL_ID SMIAPP_REG_MK_U16(0x0000)
- #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR SMIAPP_REG_MK_U8(0x0002)
-diff --git a/drivers/media/i2c/smiapp/smiapp-regs.c b/drivers/media/i2c/smiapp/smiapp-regs.c
-index 1b58b7c6c8393..904054d303ba6 100644
---- a/drivers/media/i2c/smiapp/smiapp-regs.c
-+++ b/drivers/media/i2c/smiapp/smiapp-regs.c
-@@ -133,6 +133,16 @@ static int ____smiapp_read_8only(struct smiapp_sensor *sensor, u16 reg,
- return 0;
- }
-
-+unsigned int ccs_reg_width(u32 reg)
-+{
-+ if (reg & CCS_FL_16BIT)
-+ return sizeof(uint16_t);
-+ if (reg & CCS_FL_32BIT)
-+ return sizeof(uint32_t);
-+
-+ return sizeof(uint8_t);
-+}
-+
- /*
- * Read a 8/16/32-bit i2c register. The value is returned in 'val'.
- * Returns zero if successful, or non-zero otherwise.
-@@ -141,13 +151,9 @@ static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val,
- bool only8)
- {
- struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
-- u8 len = SMIAPP_REG_WIDTH(reg);
-+ unsigned int len = ccs_reg_width(reg);
- int rval;
-
-- if (len != SMIAPP_REG_8BIT && len != SMIAPP_REG_16BIT
-- && len != SMIAPP_REG_32BIT)
-- return -EINVAL;
--
- if (!only8)
- rval = ____smiapp_read(sensor, SMIAPP_REG_ADDR(reg), len, val);
- else
-@@ -156,7 +162,7 @@ static int __smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val,
- if (rval < 0)
- return rval;
-
-- if (reg & SMIAPP_REG_FLAG_FLOAT)
-+ if (reg & CCS_FL_FLOAT_IREAL)
- *val = float_to_u32_mul_1000000(client, *val);
-
- return 0;
-@@ -204,7 +210,7 @@ int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val)
- struct i2c_msg msg;
- unsigned char data[6];
- unsigned int retries;
-- u8 len = SMIAPP_REG_WIDTH(reg);
-+ unsigned int len = ccs_reg_width(reg);
- int r;
-
- if (len > sizeof(data) - 2)
-diff --git a/drivers/media/i2c/smiapp/smiapp-regs.h b/drivers/media/i2c/smiapp/smiapp-regs.h
-index 8fda6ed5668c2..7223f5f891096 100644
---- a/drivers/media/i2c/smiapp/smiapp-regs.h
-+++ b/drivers/media/i2c/smiapp/smiapp-regs.h
-@@ -14,16 +14,9 @@
- #include <linux/i2c.h>
- #include <linux/types.h>
-
--#define SMIAPP_REG_ADDR(reg) ((u16)reg)
--#define SMIAPP_REG_WIDTH(reg) ((u8)(reg >> 16))
--#define SMIAPP_REG_FLAGS(reg) ((u8)(reg >> 24))
--
--/* Use upper 8 bits of the type field for flags */
--#define SMIAPP_REG_FLAG_FLOAT (1 << 24)
-+#include "ccs-regs.h"
-
--#define SMIAPP_REG_8BIT 1
--#define SMIAPP_REG_16BIT 2
--#define SMIAPP_REG_32BIT 4
-+#define SMIAPP_REG_ADDR(reg) ((u16)reg)
-
- struct smiapp_sensor;
-
-@@ -33,4 +26,6 @@ int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val);
- int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 val);
- int smiapp_write(struct smiapp_sensor *sensor, u32 reg, u32 val);
-
-+unsigned int ccs_reg_width(u32 reg);
-+
- #endif
---
-2.42.0
-
+++ /dev/null
-From 4d15535316eaa5027af4a7407f5238f350cfe8d2 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 11 Feb 2020 10:18:31 +0100
-Subject: media: smiapp: Use CCS registers
-
-From: Sakari Ailus <sakari.ailus@linux.intel.com>
-
-[ Upstream commit 42aab58f456a28a5d4b175e7cf7d43276ed3d06b ]
-
-Switch to CCS standard registers where they exist. The still relevant SMIA
-registers are left as-is and the redundant ones are removed.
-
-Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
-Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-Stable-dep-of: 724ff68e968b ("media: ccs: Correctly initialise try compose rectangle")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/media/i2c/smiapp/smiapp-core.c | 272 +++++++++++--------------
- drivers/media/i2c/smiapp/smiapp.h | 4 +-
- 2 files changed, 118 insertions(+), 158 deletions(-)
-
-diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
-index 2c1a135079654..8b8ef6c6d48d4 100644
---- a/drivers/media/i2c/smiapp/smiapp-core.c
-+++ b/drivers/media/i2c/smiapp/smiapp-core.c
-@@ -28,7 +28,6 @@
- #include <media/v4l2-device.h>
-
- #include "ccs-limits.h"
--#include "ccs-regs.h"
- #include "smiapp.h"
-
- #define SMIAPP_ALIGN_DIM(dim, flags) \
-@@ -367,40 +366,34 @@ static int smiapp_pll_configure(struct smiapp_sensor *sensor)
- struct smiapp_pll *pll = &sensor->pll;
- int rval;
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_VT_PIX_CLK_DIV, pll->vt.pix_clk_div);
-+ rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt.pix_clk_div);
- if (rval < 0)
- return rval;
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_VT_SYS_CLK_DIV, pll->vt.sys_clk_div);
-+ rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt.sys_clk_div);
- if (rval < 0)
- return rval;
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_PRE_PLL_CLK_DIV, pll->pre_pll_clk_div);
-+ rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->pre_pll_clk_div);
- if (rval < 0)
- return rval;
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_PLL_MULTIPLIER, pll->pll_multiplier);
-+ rval = ccs_write(sensor, PLL_MULTIPLIER, pll->pll_multiplier);
- if (rval < 0)
- return rval;
-
- /* Lane op clock ratio does not apply here. */
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS,
-- DIV_ROUND_UP(pll->op.sys_clk_freq_hz, 1000000 / 256 / 256));
-+ rval = ccs_write(sensor, REQUESTED_LINK_RATE,
-+ DIV_ROUND_UP(pll->op.sys_clk_freq_hz,
-+ 1000000 / 256 / 256));
- if (rval < 0 || sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
- return rval;
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_OP_PIX_CLK_DIV, pll->op.pix_clk_div);
-+ rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div);
- if (rval < 0)
- return rval;
-
-- return smiapp_write(
-- sensor, SMIAPP_REG_U16_OP_SYS_CLK_DIV, pll->op.sys_clk_div);
-+ return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div);
- }
-
- static int smiapp_pll_try(struct smiapp_sensor *sensor,
-@@ -532,10 +525,10 @@ static u32 smiapp_pixel_order(struct smiapp_sensor *sensor)
-
- if (sensor->hflip) {
- if (sensor->hflip->val)
-- flip |= SMIAPP_IMAGE_ORIENTATION_HFLIP;
-+ flip |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
-
- if (sensor->vflip->val)
-- flip |= SMIAPP_IMAGE_ORIENTATION_VFLIP;
-+ flip |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
- }
-
- flip ^= sensor->hvflip_inv_mask;
-@@ -595,10 +588,10 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
- return -EBUSY;
-
- if (sensor->hflip->val)
-- orient |= SMIAPP_IMAGE_ORIENTATION_HFLIP;
-+ orient |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
-
- if (sensor->vflip->val)
-- orient |= SMIAPP_IMAGE_ORIENTATION_VFLIP;
-+ orient |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
-
- orient ^= sensor->hvflip_inv_mask;
-
-@@ -643,60 +636,50 @@ static int smiapp_set_ctrl(struct v4l2_ctrl *ctrl)
-
- switch (ctrl->id) {
- case V4L2_CID_ANALOGUE_GAIN:
-- rval = smiapp_write(
-- sensor,
-- SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL, ctrl->val);
-+ rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val);
-
- break;
- case V4L2_CID_EXPOSURE:
-- rval = smiapp_write(
-- sensor,
-- SMIAPP_REG_U16_COARSE_INTEGRATION_TIME, ctrl->val);
-+ rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, ctrl->val);
-
- break;
- case V4L2_CID_HFLIP:
- case V4L2_CID_VFLIP:
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_IMAGE_ORIENTATION,
-- orient);
-+ rval = ccs_write(sensor, IMAGE_ORIENTATION, orient);
-
- break;
- case V4L2_CID_VBLANK:
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_FRAME_LENGTH_LINES,
-- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height
-- + ctrl->val);
-+ rval = ccs_write(sensor, FRAME_LENGTH_LINES,
-+ sensor->pixel_array->crop[
-+ SMIAPP_PA_PAD_SRC].height
-+ + ctrl->val);
-
- break;
- case V4L2_CID_HBLANK:
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_LINE_LENGTH_PCK,
-- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width
-- + ctrl->val);
-+ rval = ccs_write(sensor, LINE_LENGTH_PCK,
-+ sensor->pixel_array->crop[
-+ SMIAPP_PA_PAD_SRC].width
-+ + ctrl->val);
-
- break;
- case V4L2_CID_TEST_PATTERN:
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_TEST_PATTERN_MODE, ctrl->val);
-+ rval = ccs_write(sensor, TEST_PATTERN_MODE, ctrl->val);
-
- break;
- case V4L2_CID_TEST_PATTERN_RED:
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_TEST_DATA_RED, ctrl->val);
-+ rval = ccs_write(sensor, TEST_DATA_RED, ctrl->val);
-
- break;
- case V4L2_CID_TEST_PATTERN_GREENR:
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_TEST_DATA_GREENR, ctrl->val);
-+ rval = ccs_write(sensor, TEST_DATA_GREENR, ctrl->val);
-
- break;
- case V4L2_CID_TEST_PATTERN_BLUE:
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_TEST_DATA_BLUE, ctrl->val);
-+ rval = ccs_write(sensor, TEST_DATA_BLUE, ctrl->val);
-
- break;
- case V4L2_CID_TEST_PATTERN_GREENB:
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_TEST_DATA_GREENB, ctrl->val);
-+ rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val);
-
- break;
- case V4L2_CID_PIXEL_RATE:
-@@ -859,8 +842,7 @@ static int smiapp_get_mbus_formats(struct smiapp_sensor *sensor)
-
- dev_dbg(&client->dev, "data_format_model_type %d\n", type);
-
-- rval = smiapp_read(sensor, SMIAPP_REG_U8_PIXEL_ORDER,
-- &pixel_order);
-+ rval = ccs_read(sensor, PIXEL_ORDER, &pixel_order);
- if (rval)
- return rval;
-
-@@ -1068,22 +1050,20 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
-
- *status = 0;
-
-- rval = smiapp_write(sensor,
-- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT, p);
-+ rval = ccs_write(sensor, DATA_TRANSFER_IF_1_PAGE_SELECT, p);
- if (rval)
- return rval;
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL,
-- SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN);
-+ rval = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL,
-+ CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE);
- if (rval)
- return rval;
-
-- rval = smiapp_read(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS,
-- &s);
-+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
- if (rval)
- return rval;
-
-- if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE) {
-+ if (s & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE) {
- *status = s;
- return -ENODATA;
- }
-@@ -1091,14 +1071,10 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
- if (CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
- CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING) {
- for (i = 1000; i > 0; i--) {
-- if (s & SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY)
-+ if (s & CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY)
- break;
-
-- rval = smiapp_read(
-- sensor,
-- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS,
-- &s);
--
-+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
- if (rval)
- return rval;
- }
-@@ -1107,12 +1083,10 @@ static int smiapp_read_nvm_page(struct smiapp_sensor *sensor, u32 p, u8 *nvm,
- return -ETIMEDOUT;
- }
-
-- for (i = 0; i < SMIAPP_NVM_PAGE_SIZE; i++) {
-+ for (i = 0; i <= CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P; i++) {
- u32 v;
-
-- rval = smiapp_read(sensor,
-- SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 + i,
-- &v);
-+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_DATA(i), &v);
- if (rval)
- return rval;
-
-@@ -1129,20 +1103,21 @@ static int smiapp_read_nvm(struct smiapp_sensor *sensor, unsigned char *nvm,
- u32 p;
- int rval = 0, rval2;
-
-- for (p = 0; p < nvm_size / SMIAPP_NVM_PAGE_SIZE && !rval; p++) {
-+ for (p = 0; p < nvm_size / (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1)
-+ && !rval; p++) {
- rval = smiapp_read_nvm_page(sensor, p, nvm, &status);
-- nvm += SMIAPP_NVM_PAGE_SIZE;
-+ nvm += CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1;
- }
-
- if (rval == -ENODATA &&
-- status & SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE)
-+ status & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE)
- rval = 0;
-
-- rval2 = smiapp_write(sensor, SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL, 0);
-+ rval2 = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL, 0);
- if (rval < 0)
- return rval;
- else
-- return rval2 ?: p * SMIAPP_NVM_PAGE_SIZE;
-+ return rval2 ?: p * (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1);
- }
-
- /*
-@@ -1158,16 +1133,15 @@ static int smiapp_change_cci_addr(struct smiapp_sensor *sensor)
-
- client->addr = sensor->hwcfg->i2c_addr_dfl;
-
-- rval = smiapp_write(sensor,
-- SMIAPP_REG_U8_CCI_ADDRESS_CONTROL,
-- sensor->hwcfg->i2c_addr_alt << 1);
-+ rval = ccs_write(sensor, CCI_ADDRESS_CTRL,
-+ sensor->hwcfg->i2c_addr_alt << 1);
- if (rval)
- return rval;
-
- client->addr = sensor->hwcfg->i2c_addr_alt;
-
- /* verify addr change went ok */
-- rval = smiapp_read(sensor, SMIAPP_REG_U8_CCI_ADDRESS_CONTROL, &val);
-+ rval = ccs_read(sensor, CCI_ADDRESS_CTRL, &val);
- if (rval)
- return rval;
-
-@@ -1273,34 +1247,30 @@ static int smiapp_setup_flash_strobe(struct smiapp_sensor *sensor)
- strobe_width_high_rs = (tmp + strobe_adjustment - 1) /
- strobe_adjustment;
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_MODE_RS,
-- strobe_setup->mode);
-+ rval = ccs_write(sensor, FLASH_MODE_RS, strobe_setup->mode);
- if (rval < 0)
- goto out;
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT,
-- strobe_adjustment);
-+ rval = ccs_write(sensor, FLASH_STROBE_ADJUSTMENT, strobe_adjustment);
- if (rval < 0)
- goto out;
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL,
-- strobe_width_high_rs);
-+ rval = ccs_write(sensor, TFLASH_STROBE_WIDTH_HIGH_RS_CTRL,
-+ strobe_width_high_rs);
- if (rval < 0)
- goto out;
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL,
-- strobe_setup->strobe_delay);
-+ rval = ccs_write(sensor, TFLASH_STROBE_DELAY_RS_CTRL,
-+ strobe_setup->strobe_delay);
- if (rval < 0)
- goto out;
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U16_FLASH_STROBE_START_POINT,
-- strobe_setup->stobe_start_point);
-+ rval = ccs_write(sensor, FLASH_STROBE_START_POINT,
-+ strobe_setup->stobe_start_point);
- if (rval < 0)
- goto out;
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_FLASH_TRIGGER_RS,
-- strobe_setup->trigger);
-+ rval = ccs_write(sensor, FLASH_TRIGGER_RS, strobe_setup->trigger);
-
- out:
- sensor->hwcfg->strobe_setup->trigger = 0;
-@@ -1363,8 +1333,7 @@ static int smiapp_power_on(struct device *dev)
- }
- }
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_SOFTWARE_RESET,
-- SMIAPP_SOFTWARE_RESET);
-+ rval = ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
- if (rval < 0) {
- dev_err(dev, "software reset failed\n");
- goto out_cci_addr_fail;
-@@ -1378,45 +1347,42 @@ static int smiapp_power_on(struct device *dev)
- }
- }
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U16_COMPRESSION_MODE,
-- SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR);
-+ rval = ccs_write(sensor, COMPRESSION_MODE,
-+ CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE);
- if (rval) {
- dev_err(dev, "compression mode set failed\n");
- goto out_cci_addr_fail;
- }
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ,
-- sensor->hwcfg->ext_clk / (1000000 / (1 << 8)));
-+ rval = ccs_write(sensor, EXTCLK_FREQUENCY_MHZ,
-+ sensor->hwcfg->ext_clk / (1000000 / (1 << 8)));
- if (rval) {
- dev_err(dev, "extclk frequency set failed\n");
- goto out_cci_addr_fail;
- }
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_LANE_MODE,
-- sensor->hwcfg->lanes - 1);
-+ rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg->lanes - 1);
- if (rval) {
- dev_err(dev, "csi lane mode set failed\n");
- goto out_cci_addr_fail;
- }
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_FAST_STANDBY_CTRL,
-- SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE);
-+ rval = ccs_write(sensor, FAST_STANDBY_CTRL,
-+ CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION);
- if (rval) {
- dev_err(dev, "fast standby set failed\n");
- goto out_cci_addr_fail;
- }
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_CSI_SIGNALLING_MODE,
-- sensor->hwcfg->csi_signalling_mode);
-+ rval = ccs_write(sensor, CSI_SIGNALING_MODE,
-+ sensor->hwcfg->csi_signalling_mode);
- if (rval) {
- dev_err(dev, "csi signalling mode set failed\n");
- goto out_cci_addr_fail;
- }
-
- /* DPHY control done by sensor based on requested link rate */
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_DPHY_CTRL,
-- SMIAPP_DPHY_CTRL_UI);
-+ rval = ccs_write(sensor, PHY_CTRL, CCS_PHY_CTRL_UI);
- if (rval < 0)
- goto out_cci_addr_fail;
-
-@@ -1453,9 +1419,7 @@ static int smiapp_power_off(struct device *dev)
- * will fail. So do a soft reset explicitly here.
- */
- if (sensor->hwcfg->i2c_addr_alt)
-- smiapp_write(sensor,
-- SMIAPP_REG_U8_SOFTWARE_RESET,
-- SMIAPP_SOFTWARE_RESET);
-+ ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
-
- gpiod_set_value(sensor->xshutdown, 0);
- clk_disable_unprepare(sensor->ext_clk);
-@@ -1478,9 +1442,9 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
-
- mutex_lock(&sensor->mutex);
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U16_CSI_DATA_FORMAT,
-- (sensor->csi_format->width << 8) |
-- sensor->csi_format->compressed);
-+ rval = ccs_write(sensor, CSI_DATA_FORMAT,
-+ (sensor->csi_format->width << 8) |
-+ sensor->csi_format->compressed);
- if (rval)
- goto out;
-
-@@ -1493,14 +1457,13 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
- (sensor->binning_horizontal << 4)
- | sensor->binning_vertical;
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U8_BINNING_TYPE, binning_type);
-+ rval = ccs_write(sensor, BINNING_TYPE, binning_type);
- if (rval < 0)
- goto out;
-
- binning_mode = 1;
- }
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_BINNING_MODE, binning_mode);
-+ rval = ccs_write(sensor, BINNING_MODE, binning_mode);
- if (rval < 0)
- goto out;
-
-@@ -1510,26 +1473,26 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
- goto out;
-
- /* Analog crop start coordinates */
-- rval = smiapp_write(sensor, SMIAPP_REG_U16_X_ADDR_START,
-- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left);
-+ rval = ccs_write(sensor, X_ADDR_START,
-+ sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left);
- if (rval < 0)
- goto out;
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U16_Y_ADDR_START,
-- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top);
-+ rval = ccs_write(sensor, Y_ADDR_START,
-+ sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top);
- if (rval < 0)
- goto out;
-
- /* Analog crop end coordinates */
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_X_ADDR_END,
-+ rval = ccs_write(
-+ sensor, X_ADDR_END,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].left
- + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width - 1);
- if (rval < 0)
- goto out;
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_Y_ADDR_END,
-+ rval = ccs_write(
-+ sensor, Y_ADDR_END,
- sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].top
- + sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height - 1);
- if (rval < 0)
-@@ -1543,26 +1506,26 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
- /* Digital crop */
- if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
- == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET,
-+ rval = ccs_write(
-+ sensor, DIGITAL_CROP_X_OFFSET,
- sensor->scaler->crop[SMIAPP_PAD_SINK].left);
- if (rval < 0)
- goto out;
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET,
-+ rval = ccs_write(
-+ sensor, DIGITAL_CROP_Y_OFFSET,
- sensor->scaler->crop[SMIAPP_PAD_SINK].top);
- if (rval < 0)
- goto out;
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH,
-+ rval = ccs_write(
-+ sensor, DIGITAL_CROP_IMAGE_WIDTH,
- sensor->scaler->crop[SMIAPP_PAD_SINK].width);
- if (rval < 0)
- goto out;
-
-- rval = smiapp_write(
-- sensor, SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT,
-+ rval = ccs_write(
-+ sensor, DIGITAL_CROP_IMAGE_HEIGHT,
- sensor->scaler->crop[SMIAPP_PAD_SINK].height);
- if (rval < 0)
- goto out;
-@@ -1571,24 +1534,22 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
- /* Scaling */
- if (CCS_LIM(sensor, SCALING_CAPABILITY)
- != CCS_SCALING_CAPABILITY_NONE) {
-- rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALING_MODE,
-- sensor->scaling_mode);
-+ rval = ccs_write(sensor, SCALING_MODE, sensor->scaling_mode);
- if (rval < 0)
- goto out;
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U16_SCALE_M,
-- sensor->scale_m);
-+ rval = ccs_write(sensor, SCALE_M, sensor->scale_m);
- if (rval < 0)
- goto out;
- }
-
- /* Output size from sensor */
-- rval = smiapp_write(sensor, SMIAPP_REG_U16_X_OUTPUT_SIZE,
-- sensor->src->crop[SMIAPP_PAD_SRC].width);
-+ rval = ccs_write(sensor, X_OUTPUT_SIZE,
-+ sensor->src->crop[SMIAPP_PAD_SRC].width);
- if (rval < 0)
- goto out;
-- rval = smiapp_write(sensor, SMIAPP_REG_U16_Y_OUTPUT_SIZE,
-- sensor->src->crop[SMIAPP_PAD_SRC].height);
-+ rval = ccs_write(sensor, Y_OUTPUT_SIZE,
-+ sensor->src->crop[SMIAPP_PAD_SRC].height);
- if (rval < 0)
- goto out;
-
-@@ -1608,8 +1569,7 @@ static int smiapp_start_streaming(struct smiapp_sensor *sensor)
- goto out;
- }
-
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_MODE_SELECT,
-- SMIAPP_MODE_SELECT_STREAMING);
-+ rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_STREAMING);
-
- out:
- mutex_unlock(&sensor->mutex);
-@@ -1623,8 +1583,7 @@ static int smiapp_stop_streaming(struct smiapp_sensor *sensor)
- int rval;
-
- mutex_lock(&sensor->mutex);
-- rval = smiapp_write(sensor, SMIAPP_REG_U8_MODE_SELECT,
-- SMIAPP_MODE_SELECT_SOFTWARE_STANDBY);
-+ rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_SOFTWARE_STANDBY);
- if (rval)
- goto out;
-
-@@ -1842,7 +1801,7 @@ static void smiapp_propagate(struct v4l2_subdev *subdev,
- sensor->scale_m =
- CCS_LIM(sensor, SCALER_N_MIN);
- sensor->scaling_mode =
-- SMIAPP_SCALING_MODE_NONE;
-+ CCS_SCALING_MODE_NO_SCALING;
- } else if (ssd == sensor->binner) {
- sensor->binning_horizontal = 1;
- sensor->binning_vertical = 1;
-@@ -2077,7 +2036,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- u32 min, max, a, b, max_m;
- u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN);
-- int mode = SMIAPP_SCALING_MODE_HORIZONTAL;
-+ int mode = CCS_SCALING_MODE_HORIZONTAL;
- u32 try[4];
- u32 ntry = 0;
- unsigned int i;
-@@ -2137,7 +2096,7 @@ static void smiapp_set_compose_scaler(struct v4l2_subdev *subdev,
-
- if (this > best) {
- scale_m = try[i];
-- mode = SMIAPP_SCALING_MODE_HORIZONTAL;
-+ mode = CCS_SCALING_MODE_HORIZONTAL;
- best = this;
- }
-
-@@ -2508,26 +2467,24 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
- &minfo->smia_manufacturer_id);
- if (!rval)
-- rval = smiapp_read_8only(sensor, SMIAPP_REG_U16_MODEL_ID,
-+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_MODEL_ID,
- &minfo->model_id);
- if (!rval)
- rval = smiapp_read_8only(sensor,
-- SMIAPP_REG_U8_REVISION_NUMBER_MAJOR,
-+ CCS_R_MODULE_REVISION_NUMBER_MAJOR,
- &minfo->revision_number_major);
- if (!rval)
- rval = smiapp_read_8only(sensor,
-- SMIAPP_REG_U8_REVISION_NUMBER_MINOR,
-+ CCS_R_MODULE_REVISION_NUMBER_MINOR,
- &minfo->revision_number_minor);
- if (!rval)
-- rval = smiapp_read_8only(sensor,
-- SMIAPP_REG_U8_MODULE_DATE_YEAR,
-+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_YEAR,
- &minfo->module_year);
- if (!rval)
-- rval = smiapp_read_8only(sensor,
-- SMIAPP_REG_U8_MODULE_DATE_MONTH,
-+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_MONTH,
- &minfo->module_month);
- if (!rval)
-- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MODULE_DATE_DAY,
-+ rval = smiapp_read_8only(sensor, CCS_R_MODULE_DATE_DAY,
- &minfo->module_day);
-
- /* Sensor info */
-@@ -2536,19 +2493,19 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
- &minfo->sensor_mipi_manufacturer_id);
- if (!rval && !minfo->sensor_mipi_manufacturer_id)
- rval = smiapp_read_8only(sensor,
-- SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID,
-+ CCS_R_SENSOR_MANUFACTURER_ID,
- &minfo->sensor_smia_manufacturer_id);
- if (!rval)
- rval = smiapp_read_8only(sensor,
-- SMIAPP_REG_U16_SENSOR_MODEL_ID,
-+ CCS_R_SENSOR_MODEL_ID,
- &minfo->sensor_model_id);
- if (!rval)
- rval = smiapp_read_8only(sensor,
-- SMIAPP_REG_U8_SENSOR_REVISION_NUMBER,
-+ CCS_R_SENSOR_REVISION_NUMBER,
- &minfo->sensor_revision_number);
- if (!rval)
- rval = smiapp_read_8only(sensor,
-- SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION,
-+ CCS_R_SENSOR_FIRMWARE_VERSION,
- &minfo->sensor_firmware_version);
-
- /* SMIA */
-@@ -2933,7 +2890,7 @@ static struct smiapp_hwconfig *smiapp_get_hwconfig(struct device *dev)
-
- switch (bus_cfg.bus_type) {
- case V4L2_MBUS_CSI2_DPHY:
-- hwcfg->csi_signalling_mode = SMIAPP_CSI_SIGNALLING_MODE_CSI2;
-+ hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY;
- hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
- break;
- case V4L2_MBUS_CCP2:
-@@ -3109,8 +3066,9 @@ static int smiapp_probe(struct i2c_client *client)
- */
- if (sensor->hwcfg->module_board_orient ==
- SMIAPP_MODULE_BOARD_ORIENT_180)
-- sensor->hvflip_inv_mask = SMIAPP_IMAGE_ORIENTATION_HFLIP |
-- SMIAPP_IMAGE_ORIENTATION_VFLIP;
-+ sensor->hvflip_inv_mask =
-+ CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR |
-+ CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
-
- rval = smiapp_call_quirk(sensor, limits);
- if (rval) {
-diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
-index 76c29b7723fb1..3b607a2b4ca79 100644
---- a/drivers/media/i2c/smiapp/smiapp.h
-+++ b/drivers/media/i2c/smiapp/smiapp.h
-@@ -15,6 +15,8 @@
- #include <media/v4l2-ctrls.h>
- #include <media/v4l2-subdev.h>
-
-+#include "ccs-regs.h"
-+
- #include "smiapp-pll.h"
- #include "smiapp-reg.h"
- #include "smiapp-regs.h"
-@@ -220,7 +222,7 @@ struct smiapp_sensor {
- struct gpio_desc *xshutdown;
- void *ccs_limits;
- u8 nbinning_subtypes;
-- struct smiapp_binning_subtype binning_subtypes[SMIAPP_BINNING_SUBTYPES];
-+ struct smiapp_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];
- u32 mbus_frame_fmts;
- const struct smiapp_csi_data_format *csi_format;
- const struct smiapp_csi_data_format *internal_csi_format;
---
-2.42.0
-
+++ /dev/null
-From 340436e3503871d105f5e2060c0809f55293d6ea Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Mon, 3 Feb 2020 15:54:53 +0100
-Subject: media: smiapp: Use MIPI CCS version and manufacturer ID information
-
-From: Sakari Ailus <sakari.ailus@linux.intel.com>
-
-[ Upstream commit 503a88422fb0fc021b22b276f5d906eb9e7fce6e ]
-
-Read MIPI CCS manufacturer and version information, and use the CCS IDs
-over SMIA whenever they are set.
-
-Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
-Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
-Stable-dep-of: 724ff68e968b ("media: ccs: Correctly initialise try compose rectangle")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/media/i2c/smiapp/smiapp-core.c | 76 +++++++++++++++++++-------
- drivers/media/i2c/smiapp/smiapp.h | 20 ++++---
- 2 files changed, 68 insertions(+), 28 deletions(-)
-
-diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
-index 75862e7647f87..bc9c80221d2fb 100644
---- a/drivers/media/i2c/smiapp/smiapp-core.c
-+++ b/drivers/media/i2c/smiapp/smiapp-core.c
-@@ -2356,9 +2356,14 @@ smiapp_sysfs_ident_read(struct device *dev, struct device_attribute *attr,
- struct smiapp_sensor *sensor = to_smiapp_sensor(subdev);
- struct smiapp_module_info *minfo = &sensor->minfo;
-
-- return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n",
-- minfo->manufacturer_id, minfo->model_id,
-- minfo->revision_number_major) + 1;
-+ if (minfo->mipi_manufacturer_id)
-+ return snprintf(buf, PAGE_SIZE, "%4.4x%4.4x%2.2x\n",
-+ minfo->mipi_manufacturer_id, minfo->model_id,
-+ minfo->revision_number_major) + 1;
-+ else
-+ return snprintf(buf, PAGE_SIZE, "%2.2x%4.4x%2.2x\n",
-+ minfo->smia_manufacturer_id, minfo->model_id,
-+ minfo->revision_number_major) + 1;
- }
-
- static DEVICE_ATTR(ident, S_IRUGO, smiapp_sysfs_ident_read, NULL);
-@@ -2377,8 +2382,11 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
- minfo->name = SMIAPP_NAME;
-
- /* Module info */
-- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
-- &minfo->manufacturer_id);
-+ rval = ccs_read(sensor, MODULE_MANUFACTURER_ID,
-+ &minfo->mipi_manufacturer_id);
-+ if (!rval && !minfo->mipi_manufacturer_id)
-+ rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_MANUFACTURER_ID,
-+ &minfo->smia_manufacturer_id);
- if (!rval)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U16_MODEL_ID,
- &minfo->model_id);
-@@ -2404,9 +2412,12 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
-
- /* Sensor info */
- if (!rval)
-+ rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID,
-+ &minfo->sensor_mipi_manufacturer_id);
-+ if (!rval && !minfo->sensor_mipi_manufacturer_id)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID,
-- &minfo->sensor_manufacturer_id);
-+ &minfo->sensor_smia_manufacturer_id);
- if (!rval)
- rval = smiapp_read_8only(sensor,
- SMIAPP_REG_U16_SENSOR_MODEL_ID,
-@@ -2422,9 +2433,11 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
-
- /* SMIA */
- if (!rval)
-+ rval = ccs_read(sensor, MIPI_CCS_VERSION, &minfo->ccs_version);
-+ if (!rval && !minfo->ccs_version)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,
- &minfo->smia_version);
-- if (!rval)
-+ if (!rval && !minfo->ccs_version)
- rval = smiapp_read_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,
- &minfo->smiapp_version);
-
-@@ -2433,38 +2446,62 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
- return -ENODEV;
- }
-
-- dev_dbg(&client->dev, "module 0x%2.2x-0x%4.4x\n",
-- minfo->manufacturer_id, minfo->model_id);
-+ if (minfo->mipi_manufacturer_id)
-+ dev_dbg(&client->dev, "MIPI CCS module 0x%4.4x-0x%4.4x\n",
-+ minfo->mipi_manufacturer_id, minfo->model_id);
-+ else
-+ dev_dbg(&client->dev, "SMIA module 0x%2.2x-0x%4.4x\n",
-+ minfo->smia_manufacturer_id, minfo->model_id);
-
- dev_dbg(&client->dev,
- "module revision 0x%2.2x-0x%2.2x date %2.2d-%2.2d-%2.2d\n",
- minfo->revision_number_major, minfo->revision_number_minor,
- minfo->module_year, minfo->module_month, minfo->module_day);
-
-- dev_dbg(&client->dev, "sensor 0x%2.2x-0x%4.4x\n",
-- minfo->sensor_manufacturer_id, minfo->sensor_model_id);
-+ if (minfo->sensor_mipi_manufacturer_id)
-+ dev_dbg(&client->dev, "MIPI CCS sensor 0x%4.4x-0x%4.4x\n",
-+ minfo->sensor_mipi_manufacturer_id,
-+ minfo->sensor_model_id);
-+ else
-+ dev_dbg(&client->dev, "SMIA sensor 0x%2.2x-0x%4.4x\n",
-+ minfo->sensor_smia_manufacturer_id,
-+ minfo->sensor_model_id);
-
- dev_dbg(&client->dev,
- "sensor revision 0x%2.2x firmware version 0x%2.2x\n",
- minfo->sensor_revision_number, minfo->sensor_firmware_version);
-
-- dev_dbg(&client->dev, "smia version %2.2d smiapp version %2.2d\n",
-- minfo->smia_version, minfo->smiapp_version);
-+ if (minfo->ccs_version)
-+ dev_dbg(&client->dev, "MIPI CCS version %u.%u",
-+ (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MAJOR_MASK)
-+ >> CCS_MIPI_CCS_VERSION_MAJOR_SHIFT,
-+ (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MINOR_MASK));
-+ else
-+ dev_dbg(&client->dev,
-+ "smia version %2.2d smiapp version %2.2d\n",
-+ minfo->smia_version, minfo->smiapp_version);
-
- /*
- * Some modules have bad data in the lvalues below. Hope the
- * rvalues have better stuff. The lvalues are module
- * parameters whereas the rvalues are sensor parameters.
- */
-- if (!minfo->manufacturer_id && !minfo->model_id) {
-- minfo->manufacturer_id = minfo->sensor_manufacturer_id;
-+ if (minfo->sensor_smia_manufacturer_id &&
-+ !minfo->smia_manufacturer_id && !minfo->model_id) {
-+ minfo->smia_manufacturer_id =
-+ minfo->sensor_smia_manufacturer_id;
- minfo->model_id = minfo->sensor_model_id;
- minfo->revision_number_major = minfo->sensor_revision_number;
- }
-
- for (i = 0; i < ARRAY_SIZE(smiapp_module_idents); i++) {
-- if (smiapp_module_idents[i].manufacturer_id
-- != minfo->manufacturer_id)
-+ if (smiapp_module_idents[i].mipi_manufacturer_id &&
-+ smiapp_module_idents[i].mipi_manufacturer_id
-+ != minfo->mipi_manufacturer_id)
-+ continue;
-+ if (smiapp_module_idents[i].smia_manufacturer_id &&
-+ smiapp_module_idents[i].smia_manufacturer_id
-+ != minfo->smia_manufacturer_id)
- continue;
- if (smiapp_module_idents[i].model_id != minfo->model_id)
- continue;
-@@ -2488,9 +2525,8 @@ static int smiapp_identify_module(struct smiapp_sensor *sensor)
- dev_warn(&client->dev,
- "no quirks for this module; let's hope it's fully compliant\n");
-
-- dev_dbg(&client->dev, "the sensor is called %s, ident %2.2x%4.4x%2.2x\n",
-- minfo->name, minfo->manufacturer_id, minfo->model_id,
-- minfo->revision_number_major);
-+ dev_dbg(&client->dev, "the sensor is called %s\n",
-+ minfo->name);
-
- return 0;
- }
-diff --git a/drivers/media/i2c/smiapp/smiapp.h b/drivers/media/i2c/smiapp/smiapp.h
-index 6f469934f9e36..27643b36cd92b 100644
---- a/drivers/media/i2c/smiapp/smiapp.h
-+++ b/drivers/media/i2c/smiapp/smiapp.h
-@@ -91,8 +91,9 @@ struct smiapp_quirk;
- #define SMIAPP_MODULE_IDENT_FLAG_REV_LE (1 << 0)
-
- struct smiapp_module_ident {
-- u8 manufacturer_id;
-+ u16 mipi_manufacturer_id;
- u16 model_id;
-+ u8 smia_manufacturer_id;
- u8 revision_number_major;
-
- u8 flags;
-@@ -102,7 +103,8 @@ struct smiapp_module_ident {
- };
-
- struct smiapp_module_info {
-- u32 manufacturer_id;
-+ u32 smia_manufacturer_id;
-+ u32 mipi_manufacturer_id;
- u32 model_id;
- u32 revision_number_major;
- u32 revision_number_minor;
-@@ -111,13 +113,15 @@ struct smiapp_module_info {
- u32 module_month;
- u32 module_day;
-
-- u32 sensor_manufacturer_id;
-+ u32 sensor_smia_manufacturer_id;
-+ u32 sensor_mipi_manufacturer_id;
- u32 sensor_model_id;
- u32 sensor_revision_number;
- u32 sensor_firmware_version;
-
- u32 smia_version;
- u32 smiapp_version;
-+ u32 ccs_version;
-
- u32 smiapp_profile;
-
-@@ -126,7 +130,7 @@ struct smiapp_module_info {
- };
-
- #define SMIAPP_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \
-- { .manufacturer_id = manufacturer, \
-+ { .smia_manufacturer_id = manufacturer, \
- .model_id = model, \
- .revision_number_major = rev, \
- .flags = fl, \
-@@ -134,7 +138,7 @@ struct smiapp_module_info {
- .quirk = _quirk, }
-
- #define SMIAPP_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \
-- { .manufacturer_id = manufacturer, \
-+ { .smia_manufacturer_id = manufacturer, \
- .model_id = model, \
- .revision_number_major = rev, \
- .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
-@@ -142,14 +146,14 @@ struct smiapp_module_info {
- .quirk = _quirk, }
-
- #define SMIAPP_IDENT_L(manufacturer, model, rev, _name) \
-- { .manufacturer_id = manufacturer, \
-+ { .smia_manufacturer_id = manufacturer, \
- .model_id = model, \
- .revision_number_major = rev, \
- .flags = SMIAPP_MODULE_IDENT_FLAG_REV_LE, \
- .name = _name, }
-
- #define SMIAPP_IDENT_Q(manufacturer, model, rev, _name, _quirk) \
-- { .manufacturer_id = manufacturer, \
-+ { .smia_manufacturer_id = manufacturer, \
- .model_id = model, \
- .revision_number_major = rev, \
- .flags = 0, \
-@@ -157,7 +161,7 @@ struct smiapp_module_info {
- .quirk = _quirk, }
-
- #define SMIAPP_IDENT(manufacturer, model, rev, _name) \
-- { .manufacturer_id = manufacturer, \
-+ { .smia_manufacturer_id = manufacturer, \
- .model_id = model, \
- .revision_number_major = rev, \
- .flags = 0, \
---
-2.42.0
-
usb-dwc3-qcom-fix-resource-leaks-on-probe-deferral.patch
usb-dwc3-qcom-fix-acpi-platform-device-leak.patch
lockdep-fix-block-chain-corruption.patch
-media-i2c-smiapp-simplify-getting-state-container.patch
-media-smiapp-import-ccs-definitions.patch
-media-smiapp-use-ccs-register-flags.patch
-media-smiapp-calculate-ccs-limit-offsets-and-limit-b.patch
-media-smiapp-add-macros-for-accessing-ccs-registers.patch
-media-smiapp-use-mipi-ccs-version-and-manufacturer-i.patch
-media-smiapp-read-ccs-limit-values.patch
-media-smiapp-switch-to-ccs-limits.patch
-media-smiapp-use-ccs-registers.patch
media-ccs-correctly-initialise-try-compose-rectangle.patch
mips-kvm-fix-a-build-warning-about-variable-set-but-.patch
ext4-add-a-new-helper-to-check-if-es-must-be-kept.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
