arm: socfpga: vining: Fix UDC controller phandle in DT

The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
index 9e8be282005e64c5ece0e0f95ad473dbaacd1856..fb05c31d87bc517d7ba25c20818b229fe1407e6b 100644 (file)
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
@@ -11,7 +11,7 @@
 /{
        aliases {
                spi0 = "/soc/spi@ff705000";
-               udc0 = &usb0;
+               udc0 = &usb1;
        };
 };