]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: qcom: sc7180: Make watchdog bark interrupt edge triggered
authorDouglas Anderson <dianders@chromium.org>
Mon, 6 Nov 2023 22:43:28 +0000 (14:43 -0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 25 Jan 2024 23:44:47 +0000 (15:44 -0800)
[ Upstream commit 7ac90b4cf107a3999b30844d7899e0331686b33b ]

On sc7180 when the watchdog timer fires your logs get filled with:
  watchdog0: pretimeout event
  watchdog0: pretimeout event
  watchdog0: pretimeout event
  ...
  watchdog0: pretimeout event

If you're using console-ramoops to debug crashes the above gets quite
annoying since it blows away any other log messages that might have
been there.

The issue is that the "bark" interrupt (AKA the "pretimeout"
interrupt) remains high until the watchdog is pet. Since we've got
things configured as "level" triggered we'll keep getting interrupted
over and over.

Let's switch to edge triggered. Now we'll get one interrupt when the
"bark" interrupt goes off and won't get another one until the "bark"
interrupt is cleared and asserts again.

This matches how many older Qualcomm SoCs have things configured.

Fixes: 28cc13e4060c ("arm64: dts: qcom: sc7180: Add watchdog bark interrupt")
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20231106144335.v2.1.Ic7577567baff921347d423b722de8b857602efb1@changeid
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/boot/dts/qcom/sc7180.dtsi

index 11f353d416b4d585ce870cc1b3a41697f2e8e5a5..c0365832c31525c84f1668824178a9517c9a6a91 100644 (file)
                        compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
                        reg = <0 0x17c10000 0 0x1000>;
                        clocks = <&sleep_clk>;
-                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
                };
 
                timer@17c20000 {