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arm64: dts: renesas: r9a09g047: Add DMAC nodes
authorTommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Fri, 1 Aug 2025 08:48:23 +0000 (10:48 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 12 Aug 2025 07:38:53 +0000 (09:38 +0200)
Add nodes for the DMAC IPs found on the Renesas RZ/G3E SoC.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250801084825.471011-4-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/r9a09g047.dtsi patch | blob | blame | history

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index e4fac7e0d764396d47a47410ad70b86b0f603ff7..eeccd1345f71fb5d2da5a775fcccb7c34dfc416b 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -301,6 +301,176 @@
                        status = "disabled";
                };
 
+               dmac0: dma-controller@11400000 {
+                       compatible = "renesas,r9a09g047-dmac",
+                                    "renesas,r9a09g057-dmac";
+                       reg = <0 0x11400000 0 0x10000>;
+                       interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 89  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 90  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 91  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 92  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 93  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 94  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 95  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 96  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 97  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 98  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 99  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7",
+                                         "ch8", "ch9", "ch10", "ch11",
+                                         "ch12", "ch13", "ch14", "ch15";
+                       clocks = <&cpg CPG_MOD 0x0>;
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0x31>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+                       renesas,icu = <&icu 4>;
+               };
+
+               dmac1: dma-controller@14830000 {
+                       compatible = "renesas,r9a09g047-dmac",
+                                    "renesas,r9a09g057-dmac";
+                       reg = <0 0x14830000 0 0x10000>;
+                       interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 25  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 26  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 27  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 28  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 29  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 30  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 31  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 32  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 33  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 34  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 35  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 36  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 37  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 38  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 39  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 40  IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7",
+                                         "ch8", "ch9", "ch10", "ch11",
+                                         "ch12", "ch13", "ch14", "ch15";
+                       clocks = <&cpg CPG_MOD 0x1>;
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0x32>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+                       renesas,icu = <&icu 0>;
+               };
+
+               dmac2: dma-controller@14840000 {
+                       compatible = "renesas,r9a09g047-dmac",
+                                    "renesas,r9a09g057-dmac";
+                       reg = <0 0x14840000 0 0x10000>;
+                       interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 41  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 42  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 43  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 44  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 45  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 46  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 47  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 48  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 49  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 50  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 51  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 52  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 53  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 54  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 55  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 56  IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7",
+                                         "ch8", "ch9", "ch10", "ch11",
+                                         "ch12", "ch13", "ch14", "ch15";
+                       clocks = <&cpg CPG_MOD 0x2>;
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0x33>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+                       renesas,icu = <&icu 1>;
+               };
+
+               dmac3: dma-controller@12000000 {
+                       compatible = "renesas,r9a09g047-dmac",
+                                    "renesas,r9a09g057-dmac";
+                       reg = <0 0x12000000 0 0x10000>;
+                       interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 57  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 58  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 59  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 60  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 61  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 62  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 63  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 64  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 65  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 66  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 67  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 68  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 69  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 70  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 71  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 72  IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7",
+                                         "ch8", "ch9", "ch10", "ch11",
+                                         "ch12", "ch13", "ch14", "ch15";
+                       clocks = <&cpg CPG_MOD 0x3>;
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0x34>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+                       renesas,icu = <&icu 2>;
+               };
+
+               dmac4: dma-controller@12010000 {
+                       compatible = "renesas,r9a09g047-dmac",
+                                    "renesas,r9a09g057-dmac";
+                       reg = <0 0x12010000 0 0x10000>;
+                       interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 73  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 74  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 75  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 76  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 77  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 78  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 79  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 80  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 81  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 82  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 83  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 84  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 85  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 86  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 87  IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 88  IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "error",
+                                         "ch0", "ch1", "ch2", "ch3",
+                                         "ch4", "ch5", "ch6", "ch7",
+                                         "ch8", "ch9", "ch10", "ch11",
+                                         "ch12", "ch13", "ch14", "ch15";
+                       clocks = <&cpg CPG_MOD 0x4>;
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0x35>;
+                       #dma-cells = <1>;
+                       dma-channels = <16>;
+                       renesas,icu = <&icu 3>;
+               };
+
                scif0: serial@11c01400 {
                        compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057";
                        reg = <0 0x11c01400 0 0x400>;
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