accel/amdxdna: Add hardware specific attributes

Add three hardware specific attributes to describe device capabilities:
  hwctx_limit: The maximum number of hardware context supported.
  max_tops: The maximum TOPS supported.
  curr_tops: The TOPS achievable with the current power and frequency
             configuration.

Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Link: https://patch.msgid.link/20251104062546.833771-1-lizhi.hou@amd.com

diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h
index 6cc24641d3dbc6ed538164483019ac48fe2fbc10..a79f4f71ff6b644a5e399feffa2015c9b4f3c965 100644 (file)
--- a/drivers/accel/amdxdna/aie2_pci.h
+++ b/drivers/accel/amdxdna/aie2_pci.h
@@ -195,6 +195,8 @@ struct amdxdna_dev_hdl {
        u32                             clk_gating;
        u32                             npuclk_freq;
        u32                             hclk_freq;
+       u32                             max_tops;
+       u32                             curr_tops;
 
        /* Mailbox and the management channel */
        struct mailbox                  *mbox;
@@ -246,6 +248,7 @@ struct amdxdna_dev_priv {
        u32                             mbox_dev_addr;
        /* If mbox_size is 0, use BAR size. See MBOX_SIZE macro */
        u32                             mbox_size;
+       u32                             hwctx_limit;
        u32                             sram_dev_addr;
        struct aie2_bar_off_pair        sram_offs[SRAM_MAX_INDEX];
        struct aie2_bar_off_pair        psp_regs_off[PSP_MAX_REGS];

diff --git a/drivers/accel/amdxdna/aie2_smu.c b/drivers/accel/amdxdna/aie2_smu.c
index 7f292a615ed8853e4d815b49aee7f48e0304104f..11c0e9e7b03aa8996787685c2091ae27077311ef 100644 (file)
--- a/drivers/accel/amdxdna/aie2_smu.c
+++ b/drivers/accel/amdxdna/aie2_smu.c
@@ -23,6 +23,13 @@
 #define AIE2_SMU_SET_SOFT_DPMLEVEL     0x7
 #define AIE2_SMU_SET_HARD_DPMLEVEL     0x8
 
+#define NPU4_DPM_TOPS(ndev, dpm_level) \
+({ \
+       typeof(ndev) _ndev = ndev; \
+       (4096 * (_ndev)->total_col * \
+        (_ndev)->priv->dpm_clk_tbl[dpm_level].hclk / 1000000); \
+})
+
 static int aie2_smu_exec(struct amdxdna_dev_hdl *ndev, u32 reg_cmd,
                         u32 reg_arg, u32 *out)
 {
@@ -84,6 +91,8 @@ int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
        amdxdna_pm_suspend_put(ndev->xdna);
        ndev->hclk_freq = freq;
        ndev->dpm_level = dpm_level;
+       ndev->max_tops = 2 * ndev->total_col;
+       ndev->curr_tops = ndev->max_tops * freq / 1028;
 
        XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",
                 ndev->npuclk_freq, ndev->hclk_freq);
@@ -121,6 +130,8 @@ int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
        ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
        ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
        ndev->dpm_level = dpm_level;
+       ndev->max_tops = NPU4_DPM_TOPS(ndev, ndev->max_dpm_level);
+       ndev->curr_tops = NPU4_DPM_TOPS(ndev, dpm_level);
 
        XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",
                 ndev->npuclk_freq, ndev->hclk_freq);

diff --git a/drivers/accel/amdxdna/npu1_regs.c b/drivers/accel/amdxdna/npu1_regs.c
index 4a43d02404d1f16f69e63b38e7a1adc22bcfbf67..ec407f3b48fc79c42a94214ac634ae91817f1d6d 100644 (file)
--- a/drivers/accel/amdxdna/npu1_regs.c
+++ b/drivers/accel/amdxdna/npu1_regs.c
@@ -79,6 +79,7 @@ static const struct amdxdna_dev_priv npu1_dev_priv = {
        .mbox_dev_addr  = NPU1_MBOX_BAR_BASE,
        .mbox_size      = 0, /* Use BAR size */
        .sram_dev_addr  = NPU1_SRAM_BAR_BASE,
+       .hwctx_limit    = 6,
        .sram_offs      = {
                DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU1_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
                DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU1_SRAM, MPNPU_SRAM_I2X_MAILBOX_15),

diff --git a/drivers/accel/amdxdna/npu2_regs.c b/drivers/accel/amdxdna/npu2_regs.c
index 97df2f09356ab9579afd947cd163036ff11fd3b7..86f87d0d135408334ad658952684d0e5915e424d 100644 (file)
--- a/drivers/accel/amdxdna/npu2_regs.c
+++ b/drivers/accel/amdxdna/npu2_regs.c
@@ -72,6 +72,7 @@ static const struct amdxdna_dev_priv npu2_dev_priv = {
        .mbox_dev_addr  = NPU2_MBOX_BAR_BASE,
        .mbox_size      = 0, /* Use BAR size */
        .sram_dev_addr  = NPU2_SRAM_BAR_BASE,
+       .hwctx_limit    = 16,
        .sram_offs      = {
                DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
                DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),

diff --git a/drivers/accel/amdxdna/npu4_regs.c b/drivers/accel/amdxdna/npu4_regs.c
index 5a4ed0c363f851d2ade2d56f21f71bde672eebf0..d90777275a9f8481fe247380070e18d999827c24 100644 (file)
--- a/drivers/accel/amdxdna/npu4_regs.c
+++ b/drivers/accel/amdxdna/npu4_regs.c
@@ -99,6 +99,7 @@ static const struct amdxdna_dev_priv npu4_dev_priv = {
        .mbox_dev_addr  = NPU4_MBOX_BAR_BASE,
        .mbox_size      = 0, /* Use BAR size */
        .sram_dev_addr  = NPU4_SRAM_BAR_BASE,
+       .hwctx_limit    = 16,
        .sram_offs      = {
                DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
                DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),

diff --git a/drivers/accel/amdxdna/npu5_regs.c b/drivers/accel/amdxdna/npu5_regs.c
index dadd72df62637001c792a315f73ec8a10b2bf1b1..75ad97f0b9370737929c8d6fa1494e1bb65ce892 100644 (file)
--- a/drivers/accel/amdxdna/npu5_regs.c
+++ b/drivers/accel/amdxdna/npu5_regs.c
@@ -72,6 +72,7 @@ static const struct amdxdna_dev_priv npu5_dev_priv = {
        .mbox_dev_addr  = NPU5_MBOX_BAR_BASE,
        .mbox_size      = 0, /* Use BAR size */
        .sram_dev_addr  = NPU5_SRAM_BAR_BASE,
+       .hwctx_limit    = 16,
        .sram_offs      = {
                DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU5_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
                DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU5_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),

diff --git a/drivers/accel/amdxdna/npu6_regs.c b/drivers/accel/amdxdna/npu6_regs.c
index f73f92869b23358647129eb728a179972b6dbc77..758dc013fe13ba5ff3a924eaaae78c3aca823636 100644 (file)
--- a/drivers/accel/amdxdna/npu6_regs.c
+++ b/drivers/accel/amdxdna/npu6_regs.c
@@ -72,6 +72,7 @@ static const struct amdxdna_dev_priv npu6_dev_priv = {
        .mbox_dev_addr  = NPU6_MBOX_BAR_BASE,
        .mbox_size      = 0, /* Use BAR size */
        .sram_dev_addr  = NPU6_SRAM_BAR_BASE,
+       .hwctx_limit    = 16,
        .sram_offs      = {
                DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_0),
                DEFINE_BAR_OFFSET(FW_ALIVE_OFF,   NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_15),