+++ /dev/null
-/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */
-
-#ifndef _DTS_CLK_LAN9691_H
-#define _DTS_CLK_LAN9691_H
-
-#define GCK_ID_QSPI0 0
-#define GCK_ID_QSPI2 1
-#define GCK_ID_SDMMC0 2
-#define GCK_ID_SDMMC1 3
-#define GCK_ID_MCAN0 4
-#define GCK_ID_MCAN1 5
-#define GCK_ID_FLEXCOM0 6
-#define GCK_ID_FLEXCOM1 7
-#define GCK_ID_FLEXCOM2 8
-#define GCK_ID_FLEXCOM3 9
-#define GCK_ID_TIMER 10
-#define GCK_ID_USB_REFCLK 11
-
-/* Gate clocks */
-#define GCK_GATE_USB_DRD 12
-#define GCK_GATE_MCRAMC 13
-#define GCK_GATE_HMATRIX 14
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
- */
-
-#include <dt-bindings/dma/at91.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/mfd/at91-usart.h>
-#include <dt-bindings/mfd/atmel-flexcom.h>
-
-#include "clk-lan9691.h"
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- model = "Microchip LAN969x";
- compatible = "microchip,lan9691";
- interrupt-parent = <&gic>;
-
- clocks {
- fx100_clk: fx100-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <320000000>;
- };
-
- cpu_clk: cpu-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000000>;
- };
-
- ddr_clk: ddr-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <600000000>;
- };
-
- fabric_clk: fabric-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <250000000>;
- };
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53";
- device_type = "cpu";
- reg = <0x0 0x0>;
- next-level-cache = <&l2_0>;
- };
-
- l2_0: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- cache-unified;
- };
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Secure Phys IRQ */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Non-secure Phys IRQ */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virt IRQ */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hyp IRQ */
- };
-
- axi: axi {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usb: usb@300000 {
- compatible = "microchip,lan9691-dwc3", "snps,dwc3";
- reg = <0x300000 0x80000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks GCK_GATE_USB_DRD>,
- <&clks GCK_ID_USB_REFCLK>;
- clock-names = "bus_early", "ref";
- assigned-clocks = <&clks GCK_ID_USB_REFCLK>;
- assigned-clock-rates = <60000000>;
- maximum-speed = "high-speed";
- dr_mode = "host";
- status = "disabled";
- };
-
- otp: otp@e0021000 {
- compatible = "microchip,lan9691-otpc";
- reg = <0xe0021000 0x1000>;
- };
-
- flx0: flexcom@e0040000 {
- compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
- reg = <0xe0040000 0x100>;
- ranges = <0x0 0xe0040000 0x800>;
- clocks = <&clks GCK_ID_FLEXCOM0>;
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
-
- usart0: serial@200 {
- compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
- <&dma AT91_XDMAC_DT_PERID(2)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- clock-names = "usart";
- atmel,fifo-size = <32>;
- atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
- status = "disabled";
- };
-
- spi0: spi@400 {
- compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
- reg = <0x400 0x200>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
- <&dma AT91_XDMAC_DT_PERID(2)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- clock-names = "spi_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- atmel,fifo-size = <32>;
- status = "disabled";
- };
-
- i2c0: i2c@600 {
- compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
- reg = <0x600 0x200>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
- <&dma AT91_XDMAC_DT_PERID(2)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- flx1: flexcom@e0044000 {
- compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
- reg = <0xe0044000 0x100>;
- ranges = <0x0 0xe0044000 0x800>;
- clocks = <&clks GCK_ID_FLEXCOM1>;
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
-
- usart1: serial@200 {
- compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
- <&dma AT91_XDMAC_DT_PERID(2)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- clock-names = "usart";
- atmel,fifo-size = <32>;
- atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
- status = "disabled";
- };
-
- spi1: spi@400 {
- compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
- reg = <0x400 0x200>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
- <&dma AT91_XDMAC_DT_PERID(2)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- clock-names = "spi_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- atmel,fifo-size = <32>;
- status = "disabled";
- };
-
- i2c1: i2c@600 {
- compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
- reg = <0x600 0x200>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
- <&dma AT91_XDMAC_DT_PERID(2)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- trng: rng@e0048000 {
- compatible = "microchip,lan9691-trng", "atmel,at91sam9g45-trng";
- reg = <0xe0048000 0x100>;
- clocks = <&fabric_clk>;
- status = "disabled";
- };
-
- aes: crypto@e004c000 {
- compatible = "microchip,lan9691-aes", "atmel,at91sam9g46-aes";
- reg = <0xe004c000 0x100>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(12)>,
- <&dma AT91_XDMAC_DT_PERID(13)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- clock-names = "aes_clk";
- status = "disabled";
- };
-
- flx2: flexcom@e0060000 {
- compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
- reg = <0xe0060000 0x100>;
- ranges = <0x0 0xe0060000 0x800>;
- clocks = <&clks GCK_ID_FLEXCOM2>;
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
-
- usart2: serial@200 {
- compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
- <&dma AT91_XDMAC_DT_PERID(6)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- clock-names = "usart";
- atmel,fifo-size = <32>;
- atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
- status = "disabled";
- };
-
- spi2: spi@400 {
- compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
- reg = <0x400 0x200>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
- <&dma AT91_XDMAC_DT_PERID(6)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- clock-names = "spi_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- atmel,fifo-size = <32>;
- status = "disabled";
- };
-
- i2c2: i2c@600 {
- compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
- reg = <0x600 0x200>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
- <&dma AT91_XDMAC_DT_PERID(6)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- flx3: flexcom@e0064000 {
- compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
- reg = <0xe0064000 0x100>;
- ranges = <0x0 0xe0064000 0x800>;
- clocks = <&clks GCK_ID_FLEXCOM3>;
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
-
- usart3: serial@200 {
- compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
- <&dma AT91_XDMAC_DT_PERID(8)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- clock-names = "usart";
- atmel,fifo-size = <32>;
- atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
- status = "disabled";
- };
-
- spi3: spi@400 {
- compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
- reg = <0x400 0x200>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
- <&dma AT91_XDMAC_DT_PERID(8)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- clock-names = "spi_clk";
- #address-cells = <1>;
- #size-cells = <0>;
- atmel,fifo-size = <32>;
- status = "disabled";
- };
-
- i2c3: i2c@600 {
- compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
- reg = <0x600 0x200>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
- <&dma AT91_XDMAC_DT_PERID(8)>;
- dma-names = "tx", "rx";
- clocks = <&fabric_clk>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- };
-
- dma: dma-controller@e0068000 {
- compatible = "microchip,lan9691-dma", "microchip,sama7g5-dma";
- reg = <0xe0068000 0x1000>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- dma-channels = <16>;
- #dma-cells = <1>;
- clocks = <&fabric_clk>;
- clock-names = "dma_clk";
- };
-
- sha: crypto@e006c000 {
- compatible = "microchip,lan9691-sha", "atmel,at91sam9g46-sha";
- reg = <0xe006c000 0xec>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&dma AT91_XDMAC_DT_PERID(14)>;
- dma-names = "tx";
- clocks = <&fabric_clk>;
- clock-names = "sha_clk";
- status = "disabled";
- };
-
- timer: timer@e008c000 {
- compatible = "snps,dw-apb-timer";
- reg = <0xe008c000 0x400>;
- clocks = <&fabric_clk>;
- clock-names = "timer";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- watchdog: watchdog@e0090000 {
- compatible = "snps,dw-wdt";
- reg = <0xe0090000 0x1000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&fabric_clk>;
- };
-
- cpu_ctrl: syscon@e00c0000 {
- compatible = "microchip,lan966x-cpu-syscon", "syscon";
- reg = <0xe00c0000 0x350>;
- };
-
- switch: switch@e00c0000 {
- compatible = "microchip,lan9691-switch";
- reg = <0xe00c0000 0x0010000>,
- <0xe2010000 0x1410000>;
- reg-names = "cpu", "devices";
- interrupt-names = "xtr", "fdma", "ptp";
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&reset 0>;
- reset-names = "switch";
- status = "disabled";
- };
-
- clks: clock-controller@e00c00b4 {
- compatible = "microchip,lan9691-gck";
- reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>;
- #clock-cells = <1>;
- clocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>;
- clock-names = "cpu", "ddr", "sys";
- };
-
- qspi0: spi@e0804000 {
- compatible = "microchip,lan9691-qspi";
- reg = <0xe0804000 0x00000100>,
- <0x20000000 0x08000000>;
- reg-names = "qspi_base", "qspi_mmap";
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>;
- clock-names = "pclk", "gclk";
- assigned-clocks = <&clks GCK_ID_QSPI0>;
- assigned-clock-rates = <100000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sdmmc0: mmc@e0830000 {
- compatible = "microchip,lan9691-sdhci";
- reg = <0xe0830000 0x00000300>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks GCK_ID_SDMMC0>, <&clks GCK_ID_SDMMC0>;
- clock-names = "hclock", "multclk";
- assigned-clocks = <&clks GCK_ID_SDMMC0>;
- assigned-clock-rates = <100000000>;
- status = "disabled";
- };
-
- sdmmc1: mmc@e0838000 {
- compatible = "microchip,lan9691-sdhci";
- reg = <0xe0838000 0x00000300>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks GCK_ID_SDMMC1>, <&clks GCK_ID_SDMMC1>;
- clock-names = "hclock", "multclk";
- assigned-clocks = <&clks GCK_ID_SDMMC1>;
- assigned-clock-rates = <45000000>;
- status = "disabled";
- };
-
- qspi2: spi@e0834000 {
- compatible = "microchip,lan9691-qspi";
- reg = <0xe0834000 0x00000100>,
- <0x30000000 0x04000000>;
- reg-names = "qspi_base", "qspi_mmap";
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>;
- clock-names = "pclk", "gclk";
- assigned-clocks = <&clks GCK_ID_QSPI2>;
- assigned-clock-rates = <100000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- reset: reset-controller@e201000c {
- compatible = "microchip,lan9691-switch-reset",
- "microchip,lan966x-switch-reset";
- reg = <0xe201000c 0x4>;
- reg-names = "gcb";
- #reset-cells = <1>;
- cpu-syscon = <&cpu_ctrl>;
- };
-
- gpio: pinctrl@e20100d4 {
- compatible = "microchip,lan9691-pinctrl";
- reg = <0xe20100d4 0xd4>,
- <0xe2010370 0xa8>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&gpio 0 0 66>;
- interrupt-controller;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <2>;
- };
-
- mdio0: mdio@e20101a8 {
- compatible = "microchip,lan9691-miim", "mscc,ocelot-miim";
- reg = <0xe20101a8 0x24>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&fx100_clk>;
- status = "disabled";
- };
-
- mdio1: mdio@e20101cc {
- compatible = "microchip,lan9691-miim", "mscc,ocelot-miim";
- reg = <0xe20101cc 0x24>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&fx100_clk>;
- status = "disabled";
- };
-
- sgpio: gpio@e2010230 {
- compatible = "microchip,lan9691-sgpio", "microchip,sparx5-sgpio";
- reg = <0xe2010230 0x118>;
- clocks = <&fx100_clk>;
- resets = <&reset 0>;
- reset-names = "switch";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- sgpio_in: gpio@0 {
- compatible = "microchip,lan9691-sgpio-bank",
- "microchip,sparx5-sgpio-bank";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <3>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <3>;
- };
-
- sgpio_out: gpio@1 {
- compatible = "microchip,lan9691-sgpio-bank",
- "microchip,sparx5-sgpio-bank";
- reg = <1>;
- gpio-controller;
- #gpio-cells = <3>;
- };
- };
-
- tmon: hwmon@e2020100 {
- compatible = "microchip,lan9691-temp", "microchip,sparx5-temp";
- reg = <0xe2020100 0xc>;
- clocks = <&fx100_clk>;
- #thermal-sensor-cells = <0>;
- };
-
- serdes: serdes@e3410000 {
- compatible = "microchip,lan9691-serdes";
- reg = <0xe3410000 0x150000>;
- #phy-cells = <1>;
- clocks = <&fabric_clk>;
- };
-
- gic: interrupt-controller@e8c11000 {
- compatible = "arm,gic-400";
- reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */
- <0xe8c12000 0x2000>, /* CPU interface GICC_ */
- <0xe8c14000 0x2000>, /* Virt interface control */
- <0xe8c16000 0x2000>; /* Virt CPU interface */
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
-/*
- * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
- */
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include "lan9691.dtsi"
-
-/ {
- model = "Microchip EV23X71A";
- compatible = "microchip,ev23x71a", "microchip,lan9696", "microchip,lan9691";
-
- aliases {
- serial0 = &usart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&gpio 60 GPIO_ACTIVE_LOW>;
- open-source;
- priority = <200>;
- };
-
- i2c-mux {
- compatible = "i2c-mux-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- i2c-parent = <&i2c3>;
- idle-state = <0x8>;
- mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>,
- <&sgpio_out 0 2 GPIO_ACTIVE_HIGH>,
- <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>;
- settle-time-us = <100>;
-
- i2c_sfp0: i2c@0 {
- reg = <0x0>;
- };
-
- i2c_sfp1: i2c@1 {
- reg = <0x1>;
- };
-
- i2c_sfp2: i2c@2 {
- reg = <0x2>;
- };
-
- i2c_sfp3: i2c@3 {
- reg = <0x3>;
- };
-
- i2c_poe: i2c@7 {
- reg = <0x7>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-status {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio 61 GPIO_ACTIVE_LOW>;
- };
-
- led-sfp1-green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <0>;
- gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-sfp1-yellow {
- color = <LED_COLOR_ID_YELLOW>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <0>;
- gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-sfp2-green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-sfp2-yellow {
- color = <LED_COLOR_ID_YELLOW>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-sfp3-green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-sfp3-yellow {
- color = <LED_COLOR_ID_YELLOW>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-sfp4-green {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led-sfp4-yellow {
- color = <LED_COLOR_ID_YELLOW>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
- mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>,
- <&sgpio_out 1 3 GPIO_ACTIVE_LOW>;
- };
-
- sfp0: sfp0 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp0>;
- tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>;
- los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>;
- };
-
- sfp1: sfp1 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp1>;
- tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>;
- los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>;
- };
-
- sfp2: sfp2 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp2>;
- tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>;
- los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>;
- };
-
- sfp3: sfp3 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c_sfp3>;
- tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>;
- los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>;
- mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>;
- tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&gpio {
- emmc_sd_pins: emmc-sd-pins {
- /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */
- pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17",
- "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21",
- "GPIO_22", "GPIO_23", "GPIO_24";
- function = "emmc_sd";
- };
-
- fan_pins: fan-pins {
- pins = "GPIO_25", "GPIO_26";
- function = "fan";
- };
-
- fc0_pins: fc0-pins {
- pins = "GPIO_3", "GPIO_4";
- function = "fc";
- };
-
- fc2_pins: fc2-pins {
- pins = "GPIO_64", "GPIO_65", "GPIO_66";
- function = "fc";
- };
-
- fc3_pins: fc3-pins {
- pins = "GPIO_55", "GPIO_56";
- function = "fc";
- };
-
- mdio_irq_pins: mdio-irq-pins {
- pins = "GPIO_11";
- function = "miim_irq";
- };
-
- mdio_pins: mdio-pins {
- pins = "GPIO_9", "GPIO_10";
- function = "miim";
- };
-
- ptp_ext_pins: ptp-ext-pins {
- pins = "GPIO_59";
- function = "ptpsync_5";
- };
-
- ptp_out_pins: ptp-out-pins {
- pins = "GPIO_58";
- function = "ptpsync_4";
- };
-
- sgpio_pins: sgpio-pins {
- /* SCK, D0, D1, LD */
- pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8";
- function = "sgpio_a";
- };
-
- usb_over_pins: usb-over-pins {
- pins = "GPIO_13";
- function = "usb_over_detect";
- };
-
- usb_power_pins: usb-power-pins {
- pins = "GPIO_1";
- function = "usb_power";
- };
-
- usb_rst_pins: usb-rst-pins {
- pins = "GPIO_12";
- function = "usb2phy_rst";
- };
-
- usb_ulpi_pins: usb-ulpi-pins {
- pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33",
- "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37",
- "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41";
- function = "usb_ulpi";
- };
-};
-
-&flx0 {
- atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
- status = "okay";
-};
-
-&flx2 {
- atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
- status = "okay";
-};
-
-&flx3 {
- atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
- status = "okay";
-};
-
-&i2c3 {
- pinctrl-0 = <&fc3_pins>;
- pinctrl-names = "default";
- i2c-analog-filter;
- i2c-digital-filter;
- i2c-digital-filter-width-ns = <35>;
- i2c-sda-hold-time-ns = <1500>;
- status = "okay";
-};
-
-&mdio0 {
- pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>;
- pinctrl-names = "default";
- reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- phy3: phy@3 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <3>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy4: phy@4 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <4>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy5: phy@5 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <5>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy6: phy@6 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <6>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy7: phy@7 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <7>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy8: phy@8 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <8>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy9: phy@9 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <9>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy10: phy@10 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <10>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy11: phy@11 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <11>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy12: phy@12 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <12>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy13: phy@13 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <13>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy14: phy@14 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <14>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy15: phy@15 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <15>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy16: phy@16 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <16>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy17: phy@17 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <17>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy18: phy@18 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <18>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy19: phy@19 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <19>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy20: phy@20 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <20>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy21: phy@21 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <21>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy22: phy@22 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <22>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy23: phy@23 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <23>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy24: phy@24 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <24>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy25: phy@25 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <25>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy26: phy@26 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <26>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-
- phy27: phy@27 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <27>;
- interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
- interrupt-parent = <&gpio>;
- };
-};
-
-&otp {
- nvmem-layout {
- compatible = "microchip,otp-layout";
-
- base_mac_address: base-mac-address {
- #nvmem-cell-cells = <1>;
- };
- };
-};
-
-&qspi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <100000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- m25p,fast-read;
- };
-};
-
-&sdmmc0 {
- pinctrl-0 = <&emmc_sd_pins>;
- pinctrl-names = "default";
- max-frequency = <100000000>;
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- non-removable;
- disable-wp;
- status = "okay";
-};
-
-&serdes {
- status = "okay";
-};
-
-&sgpio {
- pinctrl-0 = <&sgpio_pins>;
- pinctrl-names = "default";
- microchip,sgpio-port-ranges = <0 1>, <6 9>;
- status = "okay";
-
- gpio@0 {
- ngpios = <128>;
- };
- gpio@1 {
- ngpios = <128>;
- };
-};
-
-&spi2 {
- pinctrl-0 = <&fc2_pins>;
- pinctrl-names = "default";
- cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&switch {
- pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>;
- pinctrl-names = "default";
- nvmem-cells = <&base_mac_address 0>;
- nvmem-cell-names = "mac-address";
- status = "okay";
-
- ethernet-ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port0: port@0 {
- reg = <0>;
- phy-handle = <&phy4>;
- phy-mode = "qsgmii";
- phys = <&serdes 0>;
- microchip,bandwidth = <1000>;
- };
-
- port1: port@1 {
- reg = <1>;
- phy-handle = <&phy5>;
- phy-mode = "qsgmii";
- phys = <&serdes 0>;
- microchip,bandwidth = <1000>;
- };
-
- port2: port@2 {
- reg = <2>;
- phy-handle = <&phy6>;
- phy-mode = "qsgmii";
- phys = <&serdes 0>;
- microchip,bandwidth = <1000>;
- };
-
- port3: port@3 {
- reg = <3>;
- phy-handle = <&phy7>;
- phy-mode = "qsgmii";
- phys = <&serdes 0>;
- microchip,bandwidth = <1000>;
- };
-
- port4: port@4 {
- reg = <4>;
- phy-handle = <&phy8>;
- phy-mode = "qsgmii";
- phys = <&serdes 1>;
- microchip,bandwidth = <1000>;
- };
-
- port5: port@5 {
- reg = <5>;
- phy-handle = <&phy9>;
- phy-mode = "qsgmii";
- phys = <&serdes 1>;
- microchip,bandwidth = <1000>;
- };
-
- port6: port@6 {
- reg = <6>;
- phy-handle = <&phy10>;
- phy-mode = "qsgmii";
- phys = <&serdes 1>;
- microchip,bandwidth = <1000>;
- };
-
- port7: port@7 {
- reg = <7>;
- phy-handle = <&phy11>;
- phy-mode = "qsgmii";
- phys = <&serdes 1>;
- microchip,bandwidth = <1000>;
- };
-
- port8: port@8 {
- reg = <8>;
- phy-handle = <&phy12>;
- phy-mode = "qsgmii";
- phys = <&serdes 2>;
- microchip,bandwidth = <1000>;
- };
-
- port9: port@9 {
- reg = <9>;
- phy-handle = <&phy13>;
- phy-mode = "qsgmii";
- phys = <&serdes 2>;
- microchip,bandwidth = <1000>;
- };
-
- port10: port@10 {
- reg = <10>;
- phy-handle = <&phy14>;
- phy-mode = "qsgmii";
- phys = <&serdes 2>;
- microchip,bandwidth = <1000>;
- };
-
- port11: port@11 {
- reg = <11>;
- phy-handle = <&phy15>;
- phy-mode = "qsgmii";
- phys = <&serdes 2>;
- microchip,bandwidth = <1000>;
- };
-
- port12: port@12 {
- reg = <12>;
- phy-handle = <&phy16>;
- phy-mode = "qsgmii";
- phys = <&serdes 3>;
- microchip,bandwidth = <1000>;
- };
-
- port13: port@13 {
- reg = <13>;
- phy-handle = <&phy17>;
- phy-mode = "qsgmii";
- phys = <&serdes 3>;
- microchip,bandwidth = <1000>;
- };
-
- port14: port@14 {
- reg = <14>;
- phy-handle = <&phy18>;
- phy-mode = "qsgmii";
- phys = <&serdes 3>;
- microchip,bandwidth = <1000>;
- };
-
- port15: port@15 {
- reg = <15>;
- phy-handle = <&phy19>;
- phy-mode = "qsgmii";
- phys = <&serdes 3>;
- microchip,bandwidth = <1000>;
- };
-
- port16: port@16 {
- reg = <16>;
- phy-handle = <&phy20>;
- phy-mode = "qsgmii";
- phys = <&serdes 4>;
- microchip,bandwidth = <1000>;
- };
-
- port17: port@17 {
- reg = <17>;
- phy-handle = <&phy21>;
- phy-mode = "qsgmii";
- phys = <&serdes 4>;
- microchip,bandwidth = <1000>;
- };
-
- port18: port@18 {
- reg = <18>;
- phy-handle = <&phy22>;
- phy-mode = "qsgmii";
- phys = <&serdes 4>;
- microchip,bandwidth = <1000>;
- };
-
- port19: port@19 {
- reg = <19>;
- phy-handle = <&phy23>;
- phy-mode = "qsgmii";
- phys = <&serdes 4>;
- microchip,bandwidth = <1000>;
- };
-
- port20: port@20 {
- reg = <20>;
- phy-handle = <&phy24>;
- phy-mode = "qsgmii";
- phys = <&serdes 5>;
- microchip,bandwidth = <1000>;
- };
-
- port21: port@21 {
- reg = <21>;
- phy-handle = <&phy25>;
- phy-mode = "qsgmii";
- phys = <&serdes 5>;
- microchip,bandwidth = <1000>;
- };
-
- port22: port@22 {
- reg = <22>;
- phy-handle = <&phy26>;
- phy-mode = "qsgmii";
- phys = <&serdes 5>;
- microchip,bandwidth = <1000>;
- };
-
- port23: port@23 {
- reg = <23>;
- phy-handle = <&phy27>;
- phy-mode = "qsgmii";
- phys = <&serdes 5>;
- microchip,bandwidth = <1000>;
- };
-
- port24: port@24 {
- reg = <24>;
- phys = <&serdes 6>;
- phy-mode = "10gbase-r";
- sfp = <&sfp0>;
- managed = "in-band-status";
- microchip,bandwidth = <10000>;
- microchip,sd-sgpio = <24>;
- };
-
- port25: port@25 {
- reg = <25>;
- phys = <&serdes 7>;
- phy-mode = "10gbase-r";
- sfp = <&sfp1>;
- managed = "in-band-status";
- microchip,bandwidth = <10000>;
- microchip,sd-sgpio = <28>;
- };
-
- port26: port@26 {
- reg = <26>;
- phys = <&serdes 8>;
- phy-mode = "10gbase-r";
- sfp = <&sfp2>;
- managed = "in-band-status";
- microchip,bandwidth = <10000>;
- microchip,sd-sgpio = <32>;
- };
-
- port27: port@27 {
- reg = <27>;
- phys = <&serdes 9>;
- phy-mode = "10gbase-r";
- sfp = <&sfp3>;
- managed = "in-band-status";
- microchip,bandwidth = <10000>;
- microchip,sd-sgpio = <36>;
- };
-
- port29: port@29 {
- reg = <29>;
- phy-handle = <&phy3>;
- phy-mode = "rgmii-id";
- microchip,bandwidth = <1000>;
- };
- };
-};
-
-&tmon {
- pinctrl-0 = <&fan_pins>;
- pinctrl-names = "default";
-};
-
-&usart0 {
- pinctrl-0 = <&fc0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usb {
- pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
+DTS_DIR := $(DTS_DIR)/microchip
+
define Build/lan969x-fip
cat $(STAGING_DIR_IMAGE)/$1-fip.bin >> $@
endef
DEVICE_VENDOR := Microchip
DEVICE_MODEL := EV23X71A
SOC := lan9696
+ DEVICE_DTS_DIR := $(DTS_DIR)
DEVICE_PACKAGES := kmod-i2c-mux-gpio
IMAGES += emmc-atf-gpt.gz emmc-gpt.img.gz
IMAGE/emmc-atf-gpt.gz := lan969x-gpt-emmc |\
--- /dev/null
+From 229eeb0ad913c1bb2dd6027e5983d1e4c409abd0 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Mon, 2 Mar 2026 12:20:11 +0100
+Subject: [PATCH] arm64: dts: microchip: add LAN969x clock header file
+
+LAN969x uses hardware clock indexes, so document theses in a header to make
+them humanly readable.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
+Link: https://lore.kernel.org/r/20260302112153.464422-4-robert.marko@sartura.hr
+Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
+---
+ arch/arm64/boot/dts/microchip/clk-lan9691.h | 24 +++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/microchip/clk-lan9691.h
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/microchip/clk-lan9691.h
+@@ -0,0 +1,24 @@
++/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */
++
++#ifndef _DTS_CLK_LAN9691_H
++#define _DTS_CLK_LAN9691_H
++
++#define GCK_ID_QSPI0 0
++#define GCK_ID_QSPI2 1
++#define GCK_ID_SDMMC0 2
++#define GCK_ID_SDMMC1 3
++#define GCK_ID_MCAN0 4
++#define GCK_ID_MCAN1 5
++#define GCK_ID_FLEXCOM0 6
++#define GCK_ID_FLEXCOM1 7
++#define GCK_ID_FLEXCOM2 8
++#define GCK_ID_FLEXCOM3 9
++#define GCK_ID_TIMER 10
++#define GCK_ID_USB_REFCLK 11
++
++/* Gate clocks */
++#define GCK_GATE_USB_DRD 12
++#define GCK_GATE_MCRAMC 13
++#define GCK_GATE_HMATRIX 14
++
++#endif
--- /dev/null
+From 1effec9834710ec417861634c32208edcd2fcb2a Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Mon, 2 Mar 2026 12:20:12 +0100
+Subject: [PATCH] arm64: dts: microchip: add LAN969x support
+
+Add support for Microchip LAN969x switch SoC series by adding the SoC DTSI.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
+Acked-by: Daniel Machon <daniel.machon@microchip.com>
+Link: https://lore.kernel.org/r/20260302112153.464422-5-robert.marko@sartura.hr
+Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
+---
+ arch/arm64/boot/dts/microchip/lan9691.dtsi | 488 +++++++++++++++++++++
+ 1 file changed, 488 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/microchip/lan9691.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi
+@@ -0,0 +1,488 @@
++// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
++/*
++ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
++ */
++
++#include <dt-bindings/dma/at91.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/mfd/at91-usart.h>
++#include <dt-bindings/mfd/atmel-flexcom.h>
++
++#include "clk-lan9691.h"
++
++/ {
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ model = "Microchip LAN969x";
++ compatible = "microchip,lan9691";
++ interrupt-parent = <&gic>;
++
++ clocks {
++ fx100_clk: fx100-clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <320000000>;
++ };
++
++ cpu_clk: cpu-clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <1000000000>;
++ };
++
++ ddr_clk: ddr-clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <600000000>;
++ };
++
++ fabric_clk: fabric-clk {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <250000000>;
++ };
++ };
++
++ cpus {
++ #address-cells = <2>;
++ #size-cells = <0>;
++
++ cpu0: cpu@0 {
++ compatible = "arm,cortex-a53";
++ device_type = "cpu";
++ reg = <0x0 0x0>;
++ next-level-cache = <&l2_0>;
++ };
++
++ l2_0: l2-cache {
++ compatible = "cache";
++ cache-level = <2>;
++ cache-unified;
++ };
++ };
++
++ psci {
++ compatible = "arm,psci-1.0";
++ method = "smc";
++ };
++
++ pmu {
++ compatible = "arm,cortex-a53-pmu";
++ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Secure Phys IRQ */
++ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Non-secure Phys IRQ */
++ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virt IRQ */
++ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hyp IRQ */
++ };
++
++ axi: axi {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ usb: usb@300000 {
++ compatible = "microchip,lan9691-dwc3", "snps,dwc3";
++ reg = <0x300000 0x80000>;
++ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks GCK_GATE_USB_DRD>,
++ <&clks GCK_ID_USB_REFCLK>;
++ clock-names = "bus_early", "ref";
++ assigned-clocks = <&clks GCK_ID_USB_REFCLK>;
++ assigned-clock-rates = <60000000>;
++ maximum-speed = "high-speed";
++ dr_mode = "host";
++ status = "disabled";
++ };
++
++ flx0: flexcom@e0040000 {
++ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
++ reg = <0xe0040000 0x100>;
++ ranges = <0x0 0xe0040000 0x800>;
++ clocks = <&clks GCK_ID_FLEXCOM0>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ status = "disabled";
++
++ usart0: serial@200 {
++ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
++ reg = <0x200 0x200>;
++ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
++ <&dma AT91_XDMAC_DT_PERID(2)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ clock-names = "usart";
++ atmel,fifo-size = <32>;
++ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
++ status = "disabled";
++ };
++
++ spi0: spi@400 {
++ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
++ reg = <0x400 0x200>;
++ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
++ <&dma AT91_XDMAC_DT_PERID(2)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ clock-names = "spi_clk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ atmel,fifo-size = <32>;
++ status = "disabled";
++ };
++
++ i2c0: i2c@600 {
++ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
++ reg = <0x600 0x200>;
++ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
++ <&dma AT91_XDMAC_DT_PERID(2)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ };
++
++ flx1: flexcom@e0044000 {
++ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
++ reg = <0xe0044000 0x100>;
++ ranges = <0x0 0xe0044000 0x800>;
++ clocks = <&clks GCK_ID_FLEXCOM1>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ status = "disabled";
++
++ usart1: serial@200 {
++ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
++ reg = <0x200 0x200>;
++ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
++ <&dma AT91_XDMAC_DT_PERID(2)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ clock-names = "usart";
++ atmel,fifo-size = <32>;
++ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
++ status = "disabled";
++ };
++
++ spi1: spi@400 {
++ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
++ reg = <0x400 0x200>;
++ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
++ <&dma AT91_XDMAC_DT_PERID(2)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ clock-names = "spi_clk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ atmel,fifo-size = <32>;
++ status = "disabled";
++ };
++
++ i2c1: i2c@600 {
++ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
++ reg = <0x600 0x200>;
++ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
++ <&dma AT91_XDMAC_DT_PERID(2)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ };
++
++ trng: rng@e0048000 {
++ compatible = "microchip,lan9691-trng", "atmel,at91sam9g45-trng";
++ reg = <0xe0048000 0x100>;
++ clocks = <&fabric_clk>;
++ status = "disabled";
++ };
++
++ aes: crypto@e004c000 {
++ compatible = "microchip,lan9691-aes", "atmel,at91sam9g46-aes";
++ reg = <0xe004c000 0x100>;
++ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(12)>,
++ <&dma AT91_XDMAC_DT_PERID(13)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ clock-names = "aes_clk";
++ status = "disabled";
++ };
++
++ flx2: flexcom@e0060000 {
++ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
++ reg = <0xe0060000 0x100>;
++ ranges = <0x0 0xe0060000 0x800>;
++ clocks = <&clks GCK_ID_FLEXCOM2>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ status = "disabled";
++
++ usart2: serial@200 {
++ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
++ reg = <0x200 0x200>;
++ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
++ <&dma AT91_XDMAC_DT_PERID(6)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ clock-names = "usart";
++ atmel,fifo-size = <32>;
++ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
++ status = "disabled";
++ };
++
++ spi2: spi@400 {
++ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
++ reg = <0x400 0x200>;
++ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
++ <&dma AT91_XDMAC_DT_PERID(6)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ clock-names = "spi_clk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ atmel,fifo-size = <32>;
++ status = "disabled";
++ };
++
++ i2c2: i2c@600 {
++ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
++ reg = <0x600 0x200>;
++ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
++ <&dma AT91_XDMAC_DT_PERID(6)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ };
++
++ flx3: flexcom@e0064000 {
++ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
++ reg = <0xe0064000 0x100>;
++ ranges = <0x0 0xe0064000 0x800>;
++ clocks = <&clks GCK_ID_FLEXCOM3>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ status = "disabled";
++
++ usart3: serial@200 {
++ compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
++ reg = <0x200 0x200>;
++ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
++ <&dma AT91_XDMAC_DT_PERID(8)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ clock-names = "usart";
++ atmel,fifo-size = <32>;
++ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
++ status = "disabled";
++ };
++
++ spi3: spi@400 {
++ compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
++ reg = <0x400 0x200>;
++ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
++ <&dma AT91_XDMAC_DT_PERID(8)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ clock-names = "spi_clk";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ atmel,fifo-size = <32>;
++ status = "disabled";
++ };
++
++ i2c3: i2c@600 {
++ compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
++ reg = <0x600 0x200>;
++ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
++ <&dma AT91_XDMAC_DT_PERID(8)>;
++ dma-names = "tx", "rx";
++ clocks = <&fabric_clk>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++ };
++
++ dma: dma-controller@e0068000 {
++ compatible = "microchip,lan9691-dma", "microchip,sama7g5-dma";
++ reg = <0xe0068000 0x1000>;
++ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
++ dma-channels = <16>;
++ #dma-cells = <1>;
++ clocks = <&fabric_clk>;
++ clock-names = "dma_clk";
++ };
++
++ sha: crypto@e006c000 {
++ compatible = "microchip,lan9691-sha", "atmel,at91sam9g46-sha";
++ reg = <0xe006c000 0xec>;
++ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dma AT91_XDMAC_DT_PERID(14)>;
++ dma-names = "tx";
++ clocks = <&fabric_clk>;
++ clock-names = "sha_clk";
++ status = "disabled";
++ };
++
++ timer: timer@e008c000 {
++ compatible = "snps,dw-apb-timer";
++ reg = <0xe008c000 0x400>;
++ clocks = <&fabric_clk>;
++ clock-names = "timer";
++ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ };
++
++ watchdog: watchdog@e0090000 {
++ compatible = "snps,dw-wdt";
++ reg = <0xe0090000 0x1000>;
++ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&fabric_clk>;
++ };
++
++ cpu_ctrl: syscon@e00c0000 {
++ compatible = "microchip,lan966x-cpu-syscon", "syscon";
++ reg = <0xe00c0000 0x350>;
++ };
++
++ switch: switch@e00c0000 {
++ compatible = "microchip,lan9691-switch";
++ reg = <0xe00c0000 0x0010000>,
++ <0xe2010000 0x1410000>;
++ reg-names = "cpu", "devices";
++ interrupt-names = "xtr", "fdma", "ptp";
++ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&reset 0>;
++ reset-names = "switch";
++ status = "disabled";
++ };
++
++ clks: clock-controller@e00c00b4 {
++ compatible = "microchip,lan9691-gck";
++ reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>;
++ #clock-cells = <1>;
++ clocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>;
++ clock-names = "cpu", "ddr", "sys";
++ };
++
++ reset: reset-controller@e201000c {
++ compatible = "microchip,lan9691-switch-reset",
++ "microchip,lan966x-switch-reset";
++ reg = <0xe201000c 0x4>;
++ reg-names = "gcb";
++ #reset-cells = <1>;
++ cpu-syscon = <&cpu_ctrl>;
++ };
++
++ gpio: pinctrl@e20100d4 {
++ compatible = "microchip,lan9691-pinctrl";
++ reg = <0xe20100d4 0xd4>,
++ <0xe2010370 0xa8>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&gpio 0 0 66>;
++ interrupt-controller;
++ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
++ #interrupt-cells = <2>;
++ };
++
++ mdio0: mdio@e20101a8 {
++ compatible = "microchip,lan9691-miim", "mscc,ocelot-miim";
++ reg = <0xe20101a8 0x24>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&fx100_clk>;
++ status = "disabled";
++ };
++
++ mdio1: mdio@e20101cc {
++ compatible = "microchip,lan9691-miim", "mscc,ocelot-miim";
++ reg = <0xe20101cc 0x24>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ clocks = <&fx100_clk>;
++ status = "disabled";
++ };
++
++ sgpio: gpio@e2010230 {
++ compatible = "microchip,lan9691-sgpio", "microchip,sparx5-sgpio";
++ reg = <0xe2010230 0x118>;
++ clocks = <&fx100_clk>;
++ resets = <&reset 0>;
++ reset-names = "switch";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++
++ sgpio_in: gpio@0 {
++ compatible = "microchip,lan9691-sgpio-bank",
++ "microchip,sparx5-sgpio-bank";
++ reg = <0>;
++ gpio-controller;
++ #gpio-cells = <3>;
++ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-controller;
++ #interrupt-cells = <3>;
++ };
++
++ sgpio_out: gpio@1 {
++ compatible = "microchip,lan9691-sgpio-bank",
++ "microchip,sparx5-sgpio-bank";
++ reg = <1>;
++ gpio-controller;
++ #gpio-cells = <3>;
++ };
++ };
++
++ tmon: hwmon@e2020100 {
++ compatible = "microchip,lan9691-temp", "microchip,sparx5-temp";
++ reg = <0xe2020100 0xc>;
++ clocks = <&fx100_clk>;
++ #thermal-sensor-cells = <0>;
++ };
++
++ serdes: serdes@e3410000 {
++ compatible = "microchip,lan9691-serdes";
++ reg = <0xe3410000 0x150000>;
++ #phy-cells = <1>;
++ clocks = <&fabric_clk>;
++ };
++
++ gic: interrupt-controller@e8c11000 {
++ compatible = "arm,gic-400";
++ reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */
++ <0xe8c12000 0x2000>, /* CPU interface GICC_ */
++ <0xe8c14000 0x2000>, /* Virt interface control */
++ <0xe8c16000 0x2000>; /* Virt CPU interface */
++ #interrupt-cells = <3>;
++ interrupt-controller;
++ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
++ };
++ };
++};
--- /dev/null
+From 711cca0f1cfef57018654b969da4041c2bab68d3 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Mon, 2 Mar 2026 12:20:14 +0100
+Subject: [PATCH] arm64: dts: microchip: add EV23X71A board
+
+Microchip EV23X71A is an LAN9696 based evaluation board.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
+Acked-by: Daniel Machon <daniel.machon@microchip.com>
+Tested-by: Daniel Machon <daniel.machon@microchip.com>
+Link: https://lore.kernel.org/r/20260302112153.464422-7-robert.marko@sartura.hr
+Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
+---
+ arch/arm64/boot/dts/microchip/Makefile | 1 +
+ .../boot/dts/microchip/lan9696-ev23x71a.dts | 756 ++++++++++++++++++
+ 2 files changed, 757 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts
+
+--- a/arch/arm64/boot/dts/microchip/Makefile
++++ b/arch/arm64/boot/dts/microchip/Makefile
+@@ -1,4 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_LAN969X) += lan9696-ev23x71a.dtb
+ dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb
+ dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb
+ dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts
+@@ -0,0 +1,756 @@
++// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
++/*
++ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include "lan9691.dtsi"
++
++/ {
++ model = "Microchip EV23X71A";
++ compatible = "microchip,ev23x71a", "microchip,lan9696", "microchip,lan9691";
++
++ aliases {
++ serial0 = &usart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ gpio-restart {
++ compatible = "gpio-restart";
++ gpios = <&gpio 60 GPIO_ACTIVE_LOW>;
++ open-source;
++ priority = <200>;
++ };
++
++ i2c-mux {
++ compatible = "i2c-mux-gpio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ i2c-parent = <&i2c3>;
++ idle-state = <0x8>;
++ mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>,
++ <&sgpio_out 0 2 GPIO_ACTIVE_HIGH>,
++ <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>;
++ settle-time-us = <100>;
++
++ i2c_sfp0: i2c@0 {
++ reg = <0x0>;
++ };
++
++ i2c_sfp1: i2c@1 {
++ reg = <0x1>;
++ };
++
++ i2c_sfp2: i2c@2 {
++ reg = <0x2>;
++ };
++
++ i2c_sfp3: i2c@3 {
++ reg = <0x3>;
++ };
++
++ i2c_poe: i2c@7 {
++ reg = <0x7>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ led-status {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_STATUS;
++ gpios = <&gpio 61 GPIO_ACTIVE_LOW>;
++ };
++
++ led-sfp1-green {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_LAN;
++ function-enumerator = <0>;
++ gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led-sfp1-yellow {
++ color = <LED_COLOR_ID_YELLOW>;
++ function = LED_FUNCTION_LAN;
++ function-enumerator = <0>;
++ gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led-sfp2-green {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_LAN;
++ function-enumerator = <1>;
++ gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led-sfp2-yellow {
++ color = <LED_COLOR_ID_YELLOW>;
++ function = LED_FUNCTION_LAN;
++ function-enumerator = <1>;
++ gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led-sfp3-green {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_LAN;
++ function-enumerator = <2>;
++ gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led-sfp3-yellow {
++ color = <LED_COLOR_ID_YELLOW>;
++ function = LED_FUNCTION_LAN;
++ function-enumerator = <2>;
++ gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led-sfp4-green {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_LAN;
++ function-enumerator = <3>;
++ gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ led-sfp4-yellow {
++ color = <LED_COLOR_ID_YELLOW>;
++ function = LED_FUNCTION_LAN;
++ function-enumerator = <3>;
++ gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ };
++
++ mux-controller {
++ compatible = "gpio-mux";
++ #mux-control-cells = <0>;
++ mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>,
++ <&sgpio_out 1 3 GPIO_ACTIVE_LOW>;
++ };
++
++ sfp0: sfp0 {
++ compatible = "sff,sfp";
++ i2c-bus = <&i2c_sfp0>;
++ tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>;
++ los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>;
++ mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>;
++ tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>;
++ };
++
++ sfp1: sfp1 {
++ compatible = "sff,sfp";
++ i2c-bus = <&i2c_sfp1>;
++ tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>;
++ los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>;
++ mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>;
++ tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>;
++ };
++
++ sfp2: sfp2 {
++ compatible = "sff,sfp";
++ i2c-bus = <&i2c_sfp2>;
++ tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>;
++ los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>;
++ mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>;
++ tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>;
++ };
++
++ sfp3: sfp3 {
++ compatible = "sff,sfp";
++ i2c-bus = <&i2c_sfp3>;
++ tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>;
++ los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>;
++ mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>;
++ tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>;
++ };
++};
++
++&gpio {
++ emmc_sd_pins: emmc-sd-pins {
++ /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */
++ pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17",
++ "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21",
++ "GPIO_22", "GPIO_23", "GPIO_24";
++ function = "emmc_sd";
++ };
++
++ fan_pins: fan-pins {
++ pins = "GPIO_25", "GPIO_26";
++ function = "fan";
++ };
++
++ fc0_pins: fc0-pins {
++ pins = "GPIO_3", "GPIO_4";
++ function = "fc";
++ };
++
++ fc2_pins: fc2-pins {
++ pins = "GPIO_64", "GPIO_65", "GPIO_66";
++ function = "fc";
++ };
++
++ fc3_pins: fc3-pins {
++ pins = "GPIO_55", "GPIO_56";
++ function = "fc";
++ };
++
++ mdio_irq_pins: mdio-irq-pins {
++ pins = "GPIO_11";
++ function = "miim_irq";
++ };
++
++ mdio_pins: mdio-pins {
++ pins = "GPIO_9", "GPIO_10";
++ function = "miim";
++ };
++
++ ptp_ext_pins: ptp-ext-pins {
++ pins = "GPIO_59";
++ function = "ptpsync_5";
++ };
++
++ ptp_out_pins: ptp-out-pins {
++ pins = "GPIO_58";
++ function = "ptpsync_4";
++ };
++
++ sgpio_pins: sgpio-pins {
++ /* SCK, D0, D1, LD */
++ pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8";
++ function = "sgpio_a";
++ };
++
++ usb_over_pins: usb-over-pins {
++ pins = "GPIO_13";
++ function = "usb_over_detect";
++ };
++
++ usb_power_pins: usb-power-pins {
++ pins = "GPIO_1";
++ function = "usb_power";
++ };
++
++ usb_rst_pins: usb-rst-pins {
++ pins = "GPIO_12";
++ function = "usb2phy_rst";
++ };
++
++ usb_ulpi_pins: usb-ulpi-pins {
++ pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33",
++ "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37",
++ "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41";
++ function = "usb_ulpi";
++ };
++};
++
++&flx0 {
++ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
++ status = "okay";
++};
++
++&flx2 {
++ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
++ status = "okay";
++};
++
++&flx3 {
++ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
++ status = "okay";
++};
++
++&i2c3 {
++ pinctrl-0 = <&fc3_pins>;
++ pinctrl-names = "default";
++ i2c-analog-filter;
++ i2c-digital-filter;
++ i2c-digital-filter-width-ns = <35>;
++ i2c-sda-hold-time-ns = <1500>;
++ status = "okay";
++};
++
++&mdio0 {
++ pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>;
++ pinctrl-names = "default";
++ reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>;
++ status = "okay";
++
++ phy3: phy@3 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <3>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy4: phy@4 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <4>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy5: phy@5 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <5>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy6: phy@6 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <6>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy7: phy@7 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <7>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy8: phy@8 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <8>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy9: phy@9 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <9>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy10: phy@10 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <10>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy11: phy@11 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <11>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy12: phy@12 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <12>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy13: phy@13 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <13>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy14: phy@14 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <14>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy15: phy@15 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <15>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy16: phy@16 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <16>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy17: phy@17 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <17>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy18: phy@18 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <18>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy19: phy@19 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <19>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy20: phy@20 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <20>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy21: phy@21 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <21>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy22: phy@22 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <22>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy23: phy@23 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <23>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy24: phy@24 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <24>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy25: phy@25 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <25>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy26: phy@26 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <26>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++
++ phy27: phy@27 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <27>;
++ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio>;
++ };
++};
++
++&serdes {
++ status = "okay";
++};
++
++&sgpio {
++ pinctrl-0 = <&sgpio_pins>;
++ pinctrl-names = "default";
++ microchip,sgpio-port-ranges = <0 1>, <6 9>;
++ status = "okay";
++
++ gpio@0 {
++ ngpios = <128>;
++ };
++ gpio@1 {
++ ngpios = <128>;
++ };
++};
++
++&spi2 {
++ pinctrl-0 = <&fc2_pins>;
++ pinctrl-names = "default";
++ cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&switch {
++ pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>;
++ pinctrl-names = "default";
++ status = "okay";
++
++ ethernet-ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port0: port@0 {
++ reg = <0>;
++ phy-handle = <&phy4>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 0>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port1: port@1 {
++ reg = <1>;
++ phy-handle = <&phy5>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 0>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port2: port@2 {
++ reg = <2>;
++ phy-handle = <&phy6>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 0>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port3: port@3 {
++ reg = <3>;
++ phy-handle = <&phy7>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 0>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port4: port@4 {
++ reg = <4>;
++ phy-handle = <&phy8>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 1>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port5: port@5 {
++ reg = <5>;
++ phy-handle = <&phy9>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 1>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port6: port@6 {
++ reg = <6>;
++ phy-handle = <&phy10>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 1>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port7: port@7 {
++ reg = <7>;
++ phy-handle = <&phy11>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 1>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port8: port@8 {
++ reg = <8>;
++ phy-handle = <&phy12>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 2>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port9: port@9 {
++ reg = <9>;
++ phy-handle = <&phy13>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 2>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port10: port@10 {
++ reg = <10>;
++ phy-handle = <&phy14>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 2>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port11: port@11 {
++ reg = <11>;
++ phy-handle = <&phy15>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 2>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port12: port@12 {
++ reg = <12>;
++ phy-handle = <&phy16>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 3>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port13: port@13 {
++ reg = <13>;
++ phy-handle = <&phy17>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 3>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port14: port@14 {
++ reg = <14>;
++ phy-handle = <&phy18>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 3>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port15: port@15 {
++ reg = <15>;
++ phy-handle = <&phy19>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 3>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port16: port@16 {
++ reg = <16>;
++ phy-handle = <&phy20>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 4>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port17: port@17 {
++ reg = <17>;
++ phy-handle = <&phy21>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 4>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port18: port@18 {
++ reg = <18>;
++ phy-handle = <&phy22>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 4>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port19: port@19 {
++ reg = <19>;
++ phy-handle = <&phy23>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 4>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port20: port@20 {
++ reg = <20>;
++ phy-handle = <&phy24>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 5>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port21: port@21 {
++ reg = <21>;
++ phy-handle = <&phy25>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 5>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port22: port@22 {
++ reg = <22>;
++ phy-handle = <&phy26>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 5>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port23: port@23 {
++ reg = <23>;
++ phy-handle = <&phy27>;
++ phy-mode = "qsgmii";
++ phys = <&serdes 5>;
++ microchip,bandwidth = <1000>;
++ };
++
++ port24: port@24 {
++ reg = <24>;
++ phys = <&serdes 6>;
++ phy-mode = "10gbase-r";
++ sfp = <&sfp0>;
++ managed = "in-band-status";
++ microchip,bandwidth = <10000>;
++ microchip,sd-sgpio = <24>;
++ };
++
++ port25: port@25 {
++ reg = <25>;
++ phys = <&serdes 7>;
++ phy-mode = "10gbase-r";
++ sfp = <&sfp1>;
++ managed = "in-band-status";
++ microchip,bandwidth = <10000>;
++ microchip,sd-sgpio = <28>;
++ };
++
++ port26: port@26 {
++ reg = <26>;
++ phys = <&serdes 8>;
++ phy-mode = "10gbase-r";
++ sfp = <&sfp2>;
++ managed = "in-band-status";
++ microchip,bandwidth = <10000>;
++ microchip,sd-sgpio = <32>;
++ };
++
++ port27: port@27 {
++ reg = <27>;
++ phys = <&serdes 9>;
++ phy-mode = "10gbase-r";
++ sfp = <&sfp3>;
++ managed = "in-band-status";
++ microchip,bandwidth = <10000>;
++ microchip,sd-sgpio = <36>;
++ };
++
++ port29: port@29 {
++ reg = <29>;
++ phy-handle = <&phy3>;
++ phy-mode = "rgmii-id";
++ microchip,bandwidth = <1000>;
++ };
++ };
++};
++
++&tmon {
++ pinctrl-0 = <&fan_pins>;
++ pinctrl-names = "default";
++};
++
++&usart0 {
++ pinctrl-0 = <&fc0_pins>;
++ pinctrl-names = "default";
++ status = "okay";
++};
++
++&usb {
++ pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>;
++ pinctrl-names = "default";
++ status = "okay";
++};
--- /dev/null
+From a03ebe904b22e0c3f80498fe0dbfc66090552f67 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Thu, 25 Sep 2025 22:26:13 +0200
+Subject: [PATCH 122/124] arm64: dts: microchip: lan969x: add QSPI nodes
+
+Add the required DT nodes for both QSPI controllers.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ arch/arm64/boot/dts/microchip/lan9691.dtsi | 30 ++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+--- a/arch/arm64/boot/dts/microchip/lan9691.dtsi
++++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi
+@@ -391,6 +391,36 @@
+ clock-names = "cpu", "ddr", "sys";
+ };
+
++ qspi0: spi@e0804000 {
++ compatible = "microchip,lan9691-qspi";
++ reg = <0xe0804000 0x00000100>,
++ <0x20000000 0x08000000>;
++ reg-names = "qspi_base", "qspi_mmap";
++ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>;
++ clock-names = "pclk", "gclk";
++ assigned-clocks = <&clks GCK_ID_QSPI0>;
++ assigned-clock-rates = <100000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ qspi2: spi@e0834000 {
++ compatible = "microchip,lan9691-qspi";
++ reg = <0xe0834000 0x00000100>,
++ <0x30000000 0x04000000>;
++ reg-names = "qspi_base", "qspi_mmap";
++ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>;
++ clock-names = "pclk", "gclk";
++ assigned-clocks = <&clks GCK_ID_QSPI2>;
++ assigned-clock-rates = <100000000>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
+ reset: reset-controller@e201000c {
+ compatible = "microchip,lan9691-switch-reset",
+ "microchip,lan966x-switch-reset";
--- /dev/null
+From 6751906070b6708ede20d896be7d62e19be6ef63 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Thu, 25 Sep 2025 22:26:58 +0200
+Subject: [PATCH 123/124] arm64: dts: microchip: lan969x: add SDMMC nodes
+
+Add nodes for both SDMMC controllers.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ arch/arm64/boot/dts/microchip/lan9691.dtsi | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm64/boot/dts/microchip/lan9691.dtsi
++++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi
+@@ -406,6 +406,28 @@
+ status = "disabled";
+ };
+
++ sdmmc0: mmc@e0830000 {
++ compatible = "microchip,lan9691-sdhci";
++ reg = <0xe0830000 0x00000300>;
++ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks GCK_ID_SDMMC0>, <&clks GCK_ID_SDMMC0>;
++ clock-names = "hclock", "multclk";
++ assigned-clocks = <&clks GCK_ID_SDMMC0>;
++ assigned-clock-rates = <100000000>;
++ status = "disabled";
++ };
++
++ sdmmc1: mmc@e0838000 {
++ compatible = "microchip,lan9691-sdhci";
++ reg = <0xe0838000 0x00000300>;
++ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks GCK_ID_SDMMC1>, <&clks GCK_ID_SDMMC1>;
++ clock-names = "hclock", "multclk";
++ assigned-clocks = <&clks GCK_ID_SDMMC1>;
++ assigned-clock-rates = <45000000>;
++ status = "disabled";
++ };
++
+ qspi2: spi@e0834000 {
+ compatible = "microchip,lan9691-qspi";
+ reg = <0xe0834000 0x00000100>,
--- /dev/null
+From 477b5c9af4bb7c68bd4ec4807c94dac5a90dcd2f Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Fri, 24 Oct 2025 18:46:46 +0200
+Subject: [PATCH 124/124] arm64: dts: microchip: lan969x: add OTP node
+
+Add the required OTP on LAN969x.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ arch/arm64/boot/dts/microchip/lan9691.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/boot/dts/microchip/lan9691.dtsi
++++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi
+@@ -100,6 +100,11 @@
+ status = "disabled";
+ };
+
++ otp: otp@e0021000 {
++ compatible = "microchip,lan9691-otpc";
++ reg = <0xe0021000 0x1000>;
++ };
++
+ flx0: flexcom@e0040000 {
+ compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
+ reg = <0xe0040000 0x100>;
--- /dev/null
+From 78c8a6b2d6e98dbd384e93c68779582df04fc32a Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Thu, 25 Sep 2025 22:27:58 +0200
+Subject: [PATCH] arm64: dts: microchip: ev23x71a: enable QSPI and eMMC
+
+Add the required nodes for QSPI and eMMC support.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ .../boot/dts/microchip/lan9696-ev23x71a.dts | 27 +++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts
++++ b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts
+@@ -463,6 +463,33 @@
+ };
+ };
+
++&qspi0 {
++ status = "okay";
++
++ flash@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <100000000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ spi-tx-bus-width = <1>;
++ spi-rx-bus-width = <4>;
++ m25p,fast-read;
++ };
++};
++
++&sdmmc0 {
++ pinctrl-0 = <&emmc_sd_pins>;
++ pinctrl-names = "default";
++ max-frequency = <100000000>;
++ bus-width = <8>;
++ mmc-ddr-1_8v;
++ mmc-hs200-1_8v;
++ non-removable;
++ disable-wp;
++ status = "okay";
++};
++
+ &serdes {
+ status = "okay";
+ };
projects / thirdparty / openwrt.git / commitdiff
