Subject: [PATCH] net: ethernet: mtk_eth_soc: add paths and SerDes modes for
MT7988
-MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to
-connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R,
-2500Base-X, 1000Base-X and Cisco SGMII interface modes.
+MT7988 comes with a new 10G/USXGMII SerDes PCS to connect external PHYs or
+transceivers in USXGMII, 10GBase-R and 5GBase-R interface modes in addition
+to the existing 2500Base-X, 1000Base-X and Cisco SGMII modes supported by
+the existing LynxI PCS.
-Implement support for configuring for the new paths to SerDes interfaces
-and the internal 2.5G PHY.
+Implement support for configuring for the new paths to the 10G SerDes
+interfaces.
Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and
setup the new PHYA on MT7988 to access the also still existing old
+ if (mtk_interface_mode_is_xgmii(eth, state->interface)) {
+ mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
+ mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
-+
+
+- if (mac->id == MTK_GMAC1_ID)
+- mtk_setup_bridge_switch(eth);
+ if (mac->id == MTK_GMAC1_ID)
+ mtk_setup_bridge_switch(eth);
+ } else {
+ mtk_w32(eth, 0, MTK_GDMA_EG_CTRL(mac->id));
-
-- if (mac->id == MTK_GMAC1_ID)
-- mtk_setup_bridge_switch(eth);
++
+ /* FIXME: In current hardware design, we have to reset FE
+ * when swtiching XGDM to GDM. Therefore, here trigger an SER
+ * to let GDM go back to the initial state.
/* Enable SGMII */
if (interface == PHY_INTERFACE_MODE_SGMII ||
phy_interface_mode_is_8023z(interface))
-@@ -861,7 +935,7 @@ static void mtk_xgdm_mac_link_up(struct
- int speed, int duplex, bool tx_pause,
- bool rx_pause)
- {
-- u32 mcr;
-+ u32 mcr, force_link = 0;
-
- if (mac->id == MTK_GMAC1_ID)
- return;
-@@ -872,8 +946,10 @@ static void mtk_xgdm_mac_link_up(struct
- mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR,
- MTK_XMAC_CNT_CTRL(mac->id));
-
-- mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id),
-- MTK_XGMAC_FORCE_LINK(mac->id), MTK_XGMAC_STS(mac->id));
-+ if (mac->interface == PHY_INTERFACE_MODE_INTERNAL || mac->id == MTK_GMAC3_ID)
-+ force_link = MTK_XGMAC_FORCE_LINK(mac->id);
-+
-+ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), force_link, MTK_XGMAC_STS(mac->id));
-
- mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
- mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC |
-@@ -903,6 +979,10 @@ static void mtk_mac_link_up(struct phyli
+@@ -903,6 +977,10 @@ static void mtk_mac_link_up(struct phyli
else
mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
tx_pause, rx_pause);
}
static void mtk_mac_disable_tx_lpi(struct phylink_config *config)
-@@ -3765,6 +3845,9 @@ static int mtk_open(struct net_device *d
+@@ -3765,6 +3843,9 @@ static int mtk_open(struct net_device *d
ppe_num = eth->soc->ppe_num;
err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
if (err) {
netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
-@@ -3912,6 +3995,9 @@ static int mtk_stop(struct net_device *d
+@@ -3912,6 +3993,9 @@ static int mtk_stop(struct net_device *d
for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
mtk_ppe_stop(eth->ppe[i]);
return 0;
}
-@@ -4968,6 +5054,7 @@ static const struct net_device_ops mtk_n
+@@ -4968,6 +5052,7 @@ static const struct net_device_ops mtk_n
static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
{
const __be32 *_id = of_get_property(np, "reg", NULL);
phy_interface_t phy_mode;
struct phylink *phylink;
struct mtk_mac *mac;
-@@ -5004,16 +5091,44 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -5004,16 +5089,44 @@ static int mtk_add_mac(struct mtk_eth *e
mac->id = id;
mac->hw = eth;
mac->of_node = np;
}
memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
-@@ -5099,8 +5214,21 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -5099,8 +5212,21 @@ static int mtk_add_mac(struct mtk_eth *e
phy_interface_zero(mac->phylink_config.supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
mac->phylink_config.supported_interfaces);
phylink = phylink_create(&mac->phylink_config,
of_fwnode_handle(mac->of_node),
phy_mode, &mtk_phylink_ops);
-@@ -5156,6 +5284,26 @@ free_netdev:
+@@ -5156,6 +5282,26 @@ free_netdev:
return err;
}
void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
{
struct net_device *dev, *tmp;
-@@ -5309,7 +5457,8 @@ static int mtk_probe(struct platform_dev
+@@ -5309,7 +5455,8 @@ static int mtk_probe(struct platform_dev
regmap_write(cci, 0, 3);
}
err = mtk_sgmii_init(eth);
if (err)
-@@ -5418,6 +5567,24 @@ static int mtk_probe(struct platform_dev
+@@ -5418,6 +5565,24 @@ static int mtk_probe(struct platform_dev
}
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
err = devm_request_irq(eth->dev, eth->irq[MTK_FE_IRQ_SHARED],
mtk_handle_irq, 0,
-@@ -5528,6 +5695,11 @@ static void mtk_remove(struct platform_d
+@@ -5528,6 +5693,11 @@ static void mtk_remove(struct platform_d
mtk_stop(eth->netdev[i]);
mac = netdev_priv(eth->netdev[i]);
phylink_disconnect_phy(mac->phylink);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -5733,7 +5733,7 @@ static const struct mtk_soc_data mt2701_
+@@ -5731,7 +5731,7 @@ static const struct mtk_soc_data mt2701_
DESC_SIZE(struct mtk_rx_dma),
.irq_done_mask = MTK_RX_DONE_INT,
.dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5761,7 +5761,7 @@ static const struct mtk_soc_data mt7621_
+@@ -5759,7 +5759,7 @@ static const struct mtk_soc_data mt7621_
DESC_SIZE(struct mtk_rx_dma),
.irq_done_mask = MTK_RX_DONE_INT,
.dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5791,7 +5791,7 @@ static const struct mtk_soc_data mt7622_
+@@ -5789,7 +5789,7 @@ static const struct mtk_soc_data mt7622_
DESC_SIZE(struct mtk_rx_dma),
.irq_done_mask = MTK_RX_DONE_INT,
.dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5820,7 +5820,7 @@ static const struct mtk_soc_data mt7623_
+@@ -5818,7 +5818,7 @@ static const struct mtk_soc_data mt7623_
DESC_SIZE(struct mtk_rx_dma),
.irq_done_mask = MTK_RX_DONE_INT,
.dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5846,7 +5846,7 @@ static const struct mtk_soc_data mt7629_
+@@ -5844,7 +5844,7 @@ static const struct mtk_soc_data mt7629_
DESC_SIZE(struct mtk_rx_dma),
.irq_done_mask = MTK_RX_DONE_INT,
.dma_l4_valid = RX_DMA_L4_VALID,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5878,7 +5878,7 @@ static const struct mtk_soc_data mt7981_
+@@ -5876,7 +5876,7 @@ static const struct mtk_soc_data mt7981_
.dma_l4_valid = RX_DMA_L4_VALID_V2,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
};
-@@ -5908,7 +5908,7 @@ static const struct mtk_soc_data mt7986_
+@@ -5906,7 +5906,7 @@ static const struct mtk_soc_data mt7986_
.dma_l4_valid = RX_DMA_L4_VALID_V2,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
};
-@@ -5961,7 +5961,7 @@ static const struct mtk_soc_data rt5350_
+@@ -5959,7 +5959,7 @@ static const struct mtk_soc_data rt5350_
.dma_l4_valid = RX_DMA_L4_VALID_PDMA,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
mdelay(20);
mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR,
MTK_XMAC_CNT_CTRL(mac->id));
-@@ -2984,10 +3014,16 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2982,10 +3012,16 @@ static int mtk_tx_alloc(struct mtk_eth *
mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);
val = MTK_QTX_SCH_MIN_RATE_EN |
if (mtk_is_netsys_v1(eth))
val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
-@@ -5969,6 +6005,36 @@ static const struct mtk_soc_data mt7986_
+@@ -5967,6 +6003,36 @@ static const struct mtk_soc_data mt7986_
},
};
static const struct mtk_soc_data mt7988_data = {
.reg_map = &mt7988_reg_map,
.ana_rgc3 = 0x128,
-@@ -6030,6 +6096,7 @@ const struct of_device_id of_mtk_match[]
+@@ -6028,6 +6094,7 @@ const struct of_device_id of_mtk_match[]
{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
{ .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },