drm/amd/display: Remove comparing uint32_t to zero

[WHAT]
These *bypass are uint32_t and they will never be less than zero.

Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
index 9e63fa72101cc0fe7671edef4aa72dedd1f19d3f..db687a13174d5b6aa154f6c7847e2bc77532cbd7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -509,16 +509,16 @@ void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_b
        regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10;
 
        regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
+       if (regs_and_bypass->dppclk_bypass > 4)
                regs_and_bypass->dppclk_bypass = 0;
        regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
+       if (regs_and_bypass->dcfclk_bypass > 4)
                regs_and_bypass->dcfclk_bypass = 0;
        regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
+       if (regs_and_bypass->dispclk_bypass > 4)
                regs_and_bypass->dispclk_bypass = 0;
        regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
+       if (regs_and_bypass->dprefclk_bypass > 4)
                regs_and_bypass->dprefclk_bypass = 0;
 
 }

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 1eb04772f5da29f0adef62b149f02299d28b7b7a..35d20a663d67ab8db310f1a140e3a09c655c759a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -635,16 +635,16 @@ static void dcn35_save_clk_registers(struct clk_state_registers_and_bypass *regs
        regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10;
 
        regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
+       if (regs_and_bypass->dppclk_bypass > 4)
                regs_and_bypass->dppclk_bypass = 0;
        regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
+       if (regs_and_bypass->dcfclk_bypass > 4)
                regs_and_bypass->dcfclk_bypass = 0;
        regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
+       if (regs_and_bypass->dispclk_bypass > 4)
                regs_and_bypass->dispclk_bypass = 0;
        regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
-       if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
+       if (regs_and_bypass->dprefclk_bypass > 4)
                regs_and_bypass->dprefclk_bypass = 0;
 
        if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {