ldr pc, _not_used
ldr pc, _irq
ldr pc, _fiq
-
+#ifdef CONFIG_ZYNQ_XILINX_FLASH_HEADER
+#if !defined(CONFIG_ZYNQ_XIP_START) || CONFIG_ZYNQ_XIP_START == 0
+#error CONFIG_ZYNQ_XIP_START must be defined for CONFIG_ZYNQ_XILINX_FLASH_HEADER
+#else
+/* These fields MUST immediately follow the vectors */
+#define HDR_20 0xAA995566
+#define HDR_24 0x584C4E58
+#define HDR_28 0x00000000
+#define HDR_2C 0x544F4F42
+#define HDR_30 0x00000120
+#define HDR_34 0x00000000
+#define HDR_38 0x00000000
+#define HDR_3C CONFIG_ZYNQ_XIP_START
+#define HDR_40 0x00000000
+#define HDR_44 0x00000001
+#define HDR_CSUM (~(HDR_20+HDR_24+HDR_28+HDR_2C+HDR_30+HDR_34+HDR_38+HDR_3C+HDR_40+HDR_44))
+
+.word HDR_20 /* 0xaa995566 required for sizing of the FLASH */
+.word HDR_24 /* signature 0x584C4E58 identifies the format of the image */
+.word HDR_28 /* 0xA5C3C5A3 for encrypted images */
+.word HDR_2C /* UserData can be anything */
+.word HDR_30 /* LoadStart offset into FLASH where image starts */
+.word HDR_34 /* LoadLength length of image in bytes */
+.word HDR_38 /* DestinationAddress where in OCM the image is to be written to */
+.word HDR_3C /* ImageStartAddress where to jump to at handoff (_start) */
+.word HDR_40 /* TotalImageLength - should be the same for unencrypted images */
+.word HDR_44 /* QSPIConfigWord x1 device */
+.word HDR_CSUM /* checksum - 0x20 - 0x44, complement */
+.word 0,0,0,0,0,0,0,0
+.word 0,0,0,0,0,0,0,0
+.word 0,0,0,0,0
+.word 0xFFFFFFFF /* 0xA0 */
+.word 0x00000000
+#endif
+#endif
-
+ #ifdef CONFIG_SPL_BUILD
+ _undefined_instruction: .word _undefined_instruction
+ _software_interrupt: .word _software_interrupt
+ _prefetch_abort: .word _prefetch_abort
+ _data_abort: .word _data_abort
+ _not_used: .word _not_used
+ _irq: .word _irq
+ _fiq: .word _fiq
+ _pad: .word 0x12345678 /* now 16*4=64 */
+ #else
_undefined_instruction: .word undefined_instruction
_software_interrupt: .word software_interrupt
_prefetch_abort: .word prefetch_abort
igep0020 arm armv7 igep0020 isee omap3
igep0030 arm armv7 igep0030 isee omap3
am3517_evm arm armv7 am3517evm logicpd omap3
+ mt_ventoux arm armv7 mt_ventoux teejet omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+ omap3_logic arm armv7 omap3som logicpd omap3
+ omap3_mvblx arm armv7 mvblx matrix_vision omap3
+ am3517_crane arm armv7 am3517crane ti omap3
omap3_beagle arm armv7 beagle ti omap3
omap3_evm arm armv7 evm ti omap3
+ omap3_evm_quick_mmc arm armv7 evm ti omap3
+ omap3_evm_quick_nand arm armv7 evm ti omap3
omap3_sdp3430 arm armv7 sdp3430 ti omap3
devkit8000 arm armv7 devkit8000 timll omap3
+ mcx arm armv7 mcx htkw omap3
+ tricorder arm armv7 tricorder corscience omap3
+ twister arm armv7 twister technexion omap3
omap4_panda arm armv7 panda ti omap4
omap4_sdp4430 arm armv7 sdp4430 ti omap4
+zynq_ep107 arm armv7 zynq_common xilinx zynq
+zynq_ep107_dual_qspi arm armv7 zynq_common xilinx zynq zynq_ep107:XILINX_PSS_QSPI_USE_DUAL_FLASH
+zynq_zc770_XM010 arm armv7 zynq_common xilinx zynq zynq_zc770:ZC770_XM010
+zynq_zc770_XM011 arm armv7 zynq_common xilinx zynq zynq_zc770:ZC770_XM011
+zynq_zc770_XM011_n16b arm armv7 zynq_common xilinx zynq zynq_zc770:ZC770_XM011,XILINX_ZYNQ_NAND_BUSWIDTH_16
+zynq_zc770_XM012 arm armv7 zynq_common xilinx zynq zynq_zc770:ZC770_XM012
+zynq_zc770_XM013 arm armv7 zynq_common xilinx zynq zynq_zc770:ZC770_XM013
+zynq_afx_nor arm armv7 zynq_common xilinx zynq zynq_afx:AFX_NOR
+zynq_afx_qspi arm armv7 zynq_common xilinx zynq zynq_afx:AFX_QSPI
+zynq_afx_qspi_dual arm armv7 zynq_common xilinx zynq zynq_afx:AFX_QSPI,XILINX_PSS_QSPI_USE_DUAL_FLASH
+zynq_afx_nand arm armv7 zynq_common xilinx zynq zynq_afx:AFX_NAND
+zynq_afx_nand_16b arm armv7 zynq_common xilinx zynq zynq_afx:AFX_NAND,XILINX_ZYNQ_NAND_BUSWIDTH_16
+zynq_zc702 arm armv7 zynq_common xilinx zynq
+zynq_zc706 arm armv7 zynq_common xilinx zynq
+zynq_cseflash arm armv7 zynq_common xilinx zynq
+zynq_zed arm armv7 zynq_common xilinx zynq
+ omap5_evm arm armv7 omap5_evm ti omap5
s5p_goni arm armv7 goni samsung s5pc1xx
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
- s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx
+ origen arm armv7 origen samsung exynos
+ s5pc210_universal arm armv7 universal_c210 samsung exynos
+ smdk5250 arm armv7 smdk5250 samsung exynos
+ smdkv310 arm armv7 smdkv310 samsung exynos
+ trats arm armv7 trats samsung exynos
harmony arm armv7 harmony nvidia tegra2
seaboard arm armv7 seaboard nvidia tegra2
- actux1 arm ixp
+ ventana arm armv7 ventana nvidia tegra2
+ u8500_href arm armv7 u8500 st-ericsson u8500
+ actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
+ actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
+ actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8
+ actux1_8_32 arm ixp actux1 - - actux1:FLASH1X8,RAM_32MB
actux2 arm ixp
actux3 arm ixp
actux4 arm ixp
CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
endif
- CFLAGS += $(call cc-option,-fno-stack-protector)
+# Xilinx, added to prevent unaligned accesses which started happening
+# with GCC 4.5.2 tools
+
+CFLAGS += -mno-unaligned-access
+
+ CFLAGS_SSP := $(call cc-option,-fno-stack-protector)
+ CFLAGS += $(CFLAGS_SSP)
+ # Some toolchains enable security related warning flags by default,
+ # but they don't make much sense in the u-boot world, so disable them.
+ CFLAGS_WARN := $(call cc-option,-Wno-format-nonliteral) \
+ $(call cc-option,-Wno-format-security)
+ CFLAGS += $(CFLAGS_WARN)
+
+ # Report stack usage if supported
+ CFLAGS_STACK := $(call cc-option,-fstack-usage)
+ CFLAGS += $(CFLAGS_STACK)
# $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
# option to the assembler.
COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
+ COBJS-$(CONFIG_TEGRA_I2C) += tegra_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
+ COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
+ COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
+COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+ COBJS-$(CONFIG_FTSDC010) += ftsdc010_esdhc.o
COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
+ COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o
+ COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+ COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o
COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
- COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
+ COBJS-$(CONFIG_MXS_MMC) += mxsmmc.o
COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
+ COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o
+ COBJS-$(CONFIG_SDHCI) += sdhci.o
+ COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
+ COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o
+COBJS-$(CONFIG_ZYNQ_MMC) += zynq_mmc.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
return 0x01;
}
- if (this->dev_ready) {
- if (this->dev_ready(mtd))
+/* HACK FIXME BHILL */
+#ifndef CONFIG_ZYNQ
+ if (chip->dev_ready) {
+ if (chip->dev_ready(mtd))
break;
} else {
- if (this->read_byte(mtd) & NAND_STATUS_READY)
+#endif
+ if (chip->read_byte(mtd) & NAND_STATUS_READY)
break;
+#ifndef CONFIG_ZYNQ
}
+#endif
}
#ifdef PPCHAMELON_NAND_TIMER_HACK
time_start = get_timer(0);
/* Now read the page into the buffer */
if (unlikely(ops->mode == MTD_OOB_RAW))
ret = chip->ecc.read_page_raw(mtd, chip,
- bufpoi, page);
+ bufpoi, page);
- else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
+ else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && !oob)
- ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
+ ret = chip->ecc.read_subpage(mtd, chip,
+ col, bytes, bufpoi);
else
ret = chip->ecc.read_page(mtd, chip, bufpoi,
- page);
+ page);
if (ret < 0)
break;
/* Transfer not aligned data */
if (!aligned) {
- if (!NAND_HAS_SUBPAGE_READ(chip) && !oob)
- if (!NAND_SUBPAGE_READ(chip) && !oob &&
++ if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
+ !(mtd->ecc_stats.failed - stats.failed))
chip->pagebuf = realpage;
memcpy(buf, chip->buffers->databuf + col, bytes);
}
/* Invalidate the pagebuffer reference */
chip->pagebuf = -1;
+ /* Large page NAND with SOFT_ECC should support subpage reads */
+ if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
+ chip->options |= NAND_SUBPAGE_READ;
+
/* Fill in remaining MTD driver data */
mtd->type = MTD_NANDFLASH;
- mtd->flags = MTD_CAP_NANDFLASH;
+ mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
+ MTD_CAP_NANDFLASH;
mtd->erase = nand_erase;
mtd->point = NULL;
mtd->unpoint = NULL;
#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */
#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */
- #define STM_ID_M25P10 0x11
- #define STM_ID_M25P16 0x15
- #define STM_ID_M25P20 0x12
- #define STM_ID_M25P32 0x16
- #define STM_ID_M25P40 0x13
- #define STM_ID_M25P64 0x17
- #define STM_ID_M25P80 0x14
- #define STM_ID_M25P128 0x18
-
- #define STM_ID_N25Q128 0x20BB1810
-
- #define STMICRO_SR_WIP (1 << 0) /* Write-in-Progress */
-
struct stmicro_spi_flash_params {
u8 idcode1;
+ /* XILINX: idcode1 isn't specific enough;
+ * multiple non-compatible devices match. Store complete idcode */
+ u32 idcode;
u16 page_size;
u16 pages_per_sector;
u16 nr_sectors;
.nr_sectors = 16,
.name = "M25P80",
},
- .idcode1 = STM_ID_M25P128,
- .idcode = STM_ID_N25Q128,
+/*
+ * XILINX:
+ * This table only examines the capacity of the device.
+ * The M25P128 and N25Q128 have the same capacity (16777216)
+ * but different number of sectors, pages per sector.
+ * Match the N25Q128 which is actually present on the board.
+ */
+ {
- #ifdef CONFIG_XILINX_PSS_QSPI_USE_DUAL_FLASH
- .nr_sectors = 512,
- .name = "N25Q128x2",
- #else
++ .idcode1 = 0x18,
++ .idcode = 0x20BB1810,
+ .page_size = 256,
+ .pages_per_sector = 256,
- #endif
+ .nr_sectors = 256,
+ .name = "N25Q128",
+ },
{
- .idcode1 = STM_ID_M25P128,
+ .idcode1 = 0x18,
.page_size = 256,
.pages_per_sector = 1024,
.nr_sectors = 64,
.l2_page_size = 8,
.pages_per_sector = 16,
.sectors_per_block = 16,
- #ifdef CONFIG_XILINX_PSS_QSPI_USE_DUAL_FLASH
- .nr_blocks = 512,
- .name = "W25Q128x2",
- #else
.nr_blocks = 256,
.name = "W25Q128",
- #endif
},
- .id = 0x6017,
- .l2_page_size = 8,
- .pages_per_sector = 16,
- .sectors_per_block = 16,
- #ifdef CONFIG_XILINX_PSS_QSPI_USE_DUAL_FLASH
- .nr_blocks = 256,
- .name = "W25Q64DWx2",
- #else
- .nr_blocks = 128,
- .name = "W25Q64DW",
- #endif
- }
+ {
++ .id = 0x6017,
++ .l2_page_size = 8,
++ .pages_per_sector = 16,
++ .sectors_per_block = 16,
++ .nr_blocks = 128,
++ .name = "W25Q64DW",
++ },
};
- static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout)
- {
- struct spi_slave *spi = flash->spi;
- unsigned long timebase;
- int ret;
- u8 status;
- u8 cmd[4] = { CMD_W25_RDSR, 0xff, 0xff, 0xff };
-
- ret = spi_xfer(spi, 32, &cmd[0], NULL, SPI_XFER_BEGIN);
- if (ret) {
- debug("SF: Failed to send command %02x: %d\n", cmd, ret);
- return ret;
- }
-
- timebase = get_timer(0);
- do {
- ret = spi_xfer(spi, 8, NULL, &status, 0);
- if (ret) {
- debug("SF: Failed to get status for cmd %02x: %d\n", cmd, ret);
- return -1;
- }
-
- if ((status & WINBOND_SR_WIP) == 0)
- break;
-
- } while (get_timer(timebase) < timeout);
-
- spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
-
- if ((status & WINBOND_SR_WIP) == 0)
- return 0;
-
- debug("SF: Timed out on command %02x: %d\n", cmd, ret);
- /* Timed out */
- return -1;
- }
-
- /*
- * Assemble the address part of a command for Winbond devices in
- * non-power-of-two page size mode.
- */
- static void winbond_build_address(struct winbond_spi_flash *stm, u8 *cmd, u32 offset)
- {
- unsigned long page_addr;
- unsigned long byte_addr;
- unsigned long page_size;
- unsigned int page_shift;
-
- /*
- * The "extra" space per page is the power-of-two page size
- * divided by 32.
- */
- page_shift = stm->params->l2_page_size;
- page_size = (1 << page_shift);
- page_addr = offset / page_size;
- byte_addr = offset % page_size;
-
- if (stm->addr_width == 4) {
- cmd[0] = page_addr >> (24 - page_shift);
- cmd[1] = page_addr >> (16 - page_shift);
- cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8);
- cmd[3] = byte_addr;
- } else {
- cmd[0] = page_addr >> (16 - page_shift);
- cmd[1] = page_addr << (page_shift - 8) | (byte_addr >> 8);
- cmd[2] = byte_addr;
- }
- }
-
- static inline void winbond_write_addr2cmd(struct winbond_spi_flash *stm,
- unsigned long page_addr, unsigned long byte_addr, u8 *cmd)
- {
- unsigned int page_shift;
-
- page_shift = stm->params->l2_page_size;
-
- if (stm->addr_width == 4) {
- cmd[1] = page_addr >> (24 - page_shift);
- cmd[2] = page_addr >> (16 - page_shift);
- cmd[3] = page_addr << (page_shift - 8) | (byte_addr >> 8);
- cmd[4] = byte_addr;
- } else {
- cmd[1] = page_addr >> (16 - page_shift);
- cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8);
- cmd[3] = byte_addr;
- }
- }
-
- static inline int winbond_cmdsz(struct winbond_spi_flash *flash)
+ static int winbond_erase(struct spi_flash *flash, u32 offset, size_t len)
{
- return 1 + flash->addr_width;
- }
-
- static int winbond_read_fast(struct spi_flash *flash,
- u32 offset, size_t len, void *buf)
- {
- struct winbond_spi_flash *stm = to_winbond_spi_flash(flash);
- u8 cmd[6];
-
- cmd[0] = CMD_READ_ARRAY_FAST;
- winbond_build_address(stm, cmd + 1, offset);
- cmd[winbond_cmdsz(stm)] = 0x00;
-
- return spi_flash_read_common(flash, cmd,
- winbond_cmdsz(stm)+1, buf, len);
- }
-
- static int winbond_write(struct spi_flash *flash,
- u32 offset, size_t len, const void *buf)
- {
- struct winbond_spi_flash *stm = to_winbond_spi_flash(flash);
- unsigned long page_addr;
- unsigned long byte_addr;
- unsigned long page_size;
- unsigned int page_shift;
- size_t chunk_len;
- size_t actual;
- int ret;
- u8 cmd[5];
-
- page_shift = stm->params->l2_page_size;
- page_size = (1 << page_shift);
- page_addr = offset / page_size;
- byte_addr = offset % page_size;
-
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: Unable to claim SPI bus\n");
- return ret;
- }
-
- for (actual = 0; actual < len; actual += chunk_len) {
- chunk_len = min(len - actual, page_size - byte_addr);
-
- cmd[0] = CMD_W25_PP;
- winbond_write_addr2cmd(stm, page_addr, byte_addr, cmd);
-
- debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n",
- buf + actual,
- cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
-
- ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
- if (ret < 0) {
- debug("SF: Enabling Write failed\n");
- goto out;
- }
-
- ret = spi_flash_cmd_write(flash->spi, cmd, winbond_cmdsz(stm),
- buf + actual, chunk_len);
- if (ret < 0) {
- debug("SF: Winbond Page Program failed\n");
- goto out;
- }
-
- ret = winbond_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
- if (ret < 0) {
- debug("SF: Winbond page programming timed out\n");
- goto out;
- }
-
- page_addr++;
- byte_addr = 0;
- }
-
- debug("SF: Winbond: Successfully programmed %u bytes @ 0x%x\n",
- len, offset);
- ret = 0;
-
- out:
- spi_release_bus(flash->spi);
- return ret;
- }
-
- int winbond_erase(struct spi_flash *flash, u32 offset, size_t len)
- {
- struct winbond_spi_flash *stm = to_winbond_spi_flash(flash);
- unsigned long sector_size;
- unsigned int page_shift;
- size_t actual;
- int ret;
- u8 cmd[5];
-
- /*
- * This function currently uses sector erase only.
- * probably speed things up by using bulk erase
- * when possible.
- */
-
- page_shift = stm->params->l2_page_size;
- sector_size = (1 << page_shift) * stm->params->pages_per_sector;
-
- if (offset % sector_size || len % sector_size) {
- debug("SF: Erase offset/length not multiple of sector size\n");
- return -1;
- }
-
- len /= sector_size;
- cmd[0] = CMD_W25_SE;
-
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: Unable to claim SPI bus\n");
- return ret;
- }
-
- for (actual = 0; actual < len; actual++) {
- winbond_build_address(stm, &cmd[1], offset + actual * sector_size);
-
- printf("Erase: %02x %02x %02x %02x %02x\n",
- cmd[0], cmd[1], cmd[2], cmd[3], cmd[4]);
-
- ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
- if (ret < 0) {
- debug("SF: Enabling Write failed\n");
- goto out;
- }
-
- ret = spi_flash_cmd_write(flash->spi, cmd,
- winbond_cmdsz(stm), NULL, 0);
- if (ret < 0) {
- debug("SF: Winbond sector erase failed\n");
- goto out;
- }
-
- ret = winbond_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT);
- if (ret < 0) {
- debug("SF: Winbond sector erase timed out\n");
- goto out;
- }
- }
-
- debug("SF: Winbond: Successfully erased %u bytes @ 0x%x\n",
- len * sector_size, offset);
- ret = 0;
-
- out:
- spi_release_bus(flash->spi);
- return ret;
+ return spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len);
}
struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
COBJS-$(CONFIG_ULI526X) += uli526x.o
COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
+ COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
+ COBJS-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \
+ xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o
+COBJS-$(CONFIG_ZYNQ_GEM) += zynq_gem.o zynq_gem_bdring.o zynq_gem_control.o \
+ zynq_gem_g.o zynq_gem_sinit.o zynq_gem_wrap.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
+ COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
- COBJS-$(CONFIG_TEGRA2) += serial_tegra2.o
- COBJS-$(CONFIG_USB_TTY) += usbtty.o
+COBJS-$(CONFIG_PSS_SERIAL) += serial_xpsuart.o
+ ifndef CONFIG_SPL_BUILD
+ COBJS-$(CONFIG_USB_TTY) += usbtty.o
+ endif
+
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+ COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
+ COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
+COBJS-$(CONFIG_ZYNQ_SPI) += zynq_qspi.o zynq_qspi_wrap.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
/* Chip does not allow subpage writes */
#define NAND_NO_SUBPAGE_WRITE 0x00000200
- #define NAND_SUBPAGE_READ 0x00001000
+ /* Device is one of 'new' xD cards that expose fake nand command set */
+ #define NAND_BROKEN_XD 0x00000400
+
+ /* Device behaves just like nand, but is readonly */
+ #define NAND_ROM 0x00000800
+
+/* Device supports subpage reads */
++#define NAND_SUBPAGE_READ 0x00001000
+
/* Options valid for Samsung large page devices */
#define NAND_SAMSUNG_LP_OPTIONS \
(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
-#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
- && (chip->page_shift > 9))
+ /* Large page NAND with SOFT_ECC should support subpage reads */
+#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
/* Mask to zero out the chip options, which come from the id table */
-#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
+#define NAND_CHIPOPTIONS_MSK (0x0000efff & ~NAND_NO_AUTOINCR)
/* Non chip related options */
- /* Use a flash based bad block table. This option is passed to the
- * default bad block table function. */
+ /*
+ * Use a flash based bad block table. OOB identifier is saved in OOB area.
+ * This option is passed to the default bad block table function.
+ */
#define NAND_USE_FLASH_BBT 0x00010000
/* This option skips the bbt scan during initialization. */
#define NAND_SKIP_BBTSCAN 0x00020000
int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
- int xilinx_emaclite_initialize (bd_t *bis, int base_addr);
- int sh_eth_initialize(bd_t *bis);
- int dm9000_initialize(bd_t *bis);
- int fecmxc_initialize(bd_t *bis);
- int zynq_gem_initialize(bd_t *bis);
+ int armada100_fec_register(unsigned long base_addr);
+ int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
+ unsigned long dma_addr);
+ int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
+ int txpp, int rxpp);
+ int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
+ unsigned long ctrl_addr);
++int zynq_gem_initialize(bd_t *bis);
+
+ /*
+ * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
+ * exported by a public hader file, we need a global definition at this point.
+ */
+ #if defined(CONFIG_XILINX_LL_TEMAC)
+ #define XILINX_LL_TEMAC_M_FIFO 0 /* use FIFO Ctrl */
+ #define XILINX_LL_TEMAC_M_SDMA_PLB (1 << 0)/* use SDMA Ctrl via PLB */
+ #define XILINX_LL_TEMAC_M_SDMA_DCR (1 << 1)/* use SDMA Ctrl via DCR */
+ #endif
/* Boards with PCI network controllers can call this from their board_eth_init()
* function to initialize whatever's on board.
projects / thirdparty / u-boot.git / commitdiff
