arm64: dts: ti: k3-j7200-ti-ipc-firmware: Refactor IPC cfg into new dtsi

The TI K3 J7200 SoCs have multiple programmable remote processors like
R5Fs. The TI SDKs for J7200 SoCs offer sample firmwares which could be
run on these cores to demonstrate an "echo" IPC test. Those firmware
require certain memory carveouts to be reserved from system memory,
timers to be reserved, and certain mailbox configurations for interrupt
based messaging. These configurations could be different for a different
firmware.

While DT is not meant for system configurations, at least refactor these
configurations from board level DTS into a dtsi for now. This dtsi for
TI IPC firmware is board-independent and can be applied to all boards
from the same SoC Family. This gets rid of code duplication and allows
more freedom for users developing custom firmware (or no firmware) to
utilize system resources better; easily by swapping out this dtsi. To
maintain backward compatibility, the dtsi is included in all boards.

Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://patch.msgid.link/20250908142826.1828676-25-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
index c689e417cf458464b47ddc6652c152d2509e8cc4..5a8c2e707fde945588412d1a9374fbd4199d1c55 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -40,48 +40,6 @@
                        reg = <0x00 0xa0100000 0x00 0xf00000>;
                        no-map;
                };
-
-               mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa1000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               mcu_r5fss0_core1_memory_region: memory@a1100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa1100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               main_r5fss0_core0_dma_memory_region: memory@a2000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa2000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               main_r5fss0_core0_memory_region: memory@a2100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa2100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               main_r5fss0_core1_dma_memory_region: memory@a3000000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa3000000 0x00 0x100000>;
-                       no-map;
-               };
-
-               main_r5fss0_core1_memory_region: memory@a3100000 {
-                       compatible = "shared-dma-pool";
-                       reg = <0x00 0xa3100000 0x00 0xf00000>;
-                       no-map;
-               };
-
-               rtos_ipc_memory_region: memory@a4000000 {
-                       reg = <0x00 0xa4000000 0x00 0x00800000>;
-                       alignment = <0x1000>;
-                       no-map;
-               };
        };
 
        mux0: mux-controller-0 {
@@ -224,86 +182,6 @@
        };
 };
 
-&mailbox0_cluster0 {
-       status = "okay";
-       interrupts = <436>;
-
-       mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
-               ti,mbox-rx = <0 0 0>;
-               ti,mbox-tx = <1 0 0>;
-       };
-
-       mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
-               ti,mbox-rx = <2 0 0>;
-               ti,mbox-tx = <3 0 0>;
-       };
-};
-
-&mailbox0_cluster1 {
-       status = "okay";
-       interrupts = <432>;
-
-       mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
-               ti,mbox-rx = <0 0 0>;
-               ti,mbox-tx = <1 0 0>;
-       };
-
-       mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
-               ti,mbox-rx = <2 0 0>;
-               ti,mbox-tx = <3 0 0>;
-       };
-};
-
-&mcu_r5fss0 {
-       status = "okay";
-};
-
-&mcu_r5fss0_core0 {
-       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
-       memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
-                       <&mcu_r5fss0_core0_memory_region>;
-       status = "okay";
-};
-
-&mcu_r5fss0_core1 {
-       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
-       memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
-                       <&mcu_r5fss0_core1_memory_region>;
-       status = "okay";
-};
-
-&main_r5fss0 {
-       ti,cluster-mode = <0>;
-       status = "okay";
-};
-
-/* Timers are used by Remoteproc firmware */
-&main_timer0 {
-       status = "reserved";
-};
-
-&main_timer1 {
-       status = "reserved";
-};
-
-&main_timer2 {
-       status = "reserved";
-};
-
-&main_r5fss0_core0 {
-       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
-       memory-region = <&main_r5fss0_core0_dma_memory_region>,
-                       <&main_r5fss0_core0_memory_region>;
-       status = "okay";
-};
-
-&main_r5fss0_core1 {
-       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
-       memory-region = <&main_r5fss0_core1_dma_memory_region>,
-                       <&main_r5fss0_core1_memory_region>;
-       status = "okay";
-};
-
 &main_i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_i2c0_pins_default>;
@@ -546,3 +424,5 @@
        pinctrl-names = "default";
        phys = <&transceiver0>;
 };
+
+#include "k3-j7200-ti-ipc-firmware.dtsi"

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi
new file mode 100644 (file)
index 0000000..9477f1e
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * Device Tree Source for enabling IPC using TI SDK firmware on J7200 SoCs
+ *
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&reserved_memory {
+       mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
+               compatible = "shared-dma-pool";
+               reg = <0x00 0xa1000000 0x00 0x100000>;
+               no-map;
+       };
+
+       mcu_r5fss0_core1_memory_region: memory@a1100000 {
+               compatible = "shared-dma-pool";
+               reg = <0x00 0xa1100000 0x00 0xf00000>;
+               no-map;
+       };
+
+       main_r5fss0_core0_dma_memory_region: memory@a2000000 {
+               compatible = "shared-dma-pool";
+               reg = <0x00 0xa2000000 0x00 0x100000>;
+               no-map;
+       };
+
+       main_r5fss0_core0_memory_region: memory@a2100000 {
+               compatible = "shared-dma-pool";
+               reg = <0x00 0xa2100000 0x00 0xf00000>;
+               no-map;
+       };
+
+       main_r5fss0_core1_dma_memory_region: memory@a3000000 {
+               compatible = "shared-dma-pool";
+               reg = <0x00 0xa3000000 0x00 0x100000>;
+               no-map;
+       };
+
+       main_r5fss0_core1_memory_region: memory@a3100000 {
+               compatible = "shared-dma-pool";
+               reg = <0x00 0xa3100000 0x00 0xf00000>;
+               no-map;
+       };
+
+       rtos_ipc_memory_region: memory@a4000000 {
+               reg = <0x00 0xa4000000 0x00 0x00800000>;
+               alignment = <0x1000>;
+               no-map;
+       };
+};
+
+&mailbox0_cluster0 {
+       status = "okay";
+       interrupts = <436>;
+
+       mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+&mailbox0_cluster1 {
+       status = "okay";
+       interrupts = <432>;
+
+       mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+               ti,mbox-rx = <0 0 0>;
+               ti,mbox-tx = <1 0 0>;
+       };
+
+       mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+               ti,mbox-rx = <2 0 0>;
+               ti,mbox-tx = <3 0 0>;
+       };
+};
+
+/* Timers are used by Remoteproc firmware */
+&main_timer0 {
+       status = "reserved";
+};
+
+&main_timer1 {
+       status = "reserved";
+};
+
+&main_timer2 {
+       status = "reserved";
+};
+
+&mcu_r5fss0 {
+       status = "okay";
+};
+
+&mcu_r5fss0_core0 {
+       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+       memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+                       <&mcu_r5fss0_core0_memory_region>;
+       status = "okay";
+};
+
+&mcu_r5fss0_core1 {
+       mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+       memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+                       <&mcu_r5fss0_core1_memory_region>;
+       status = "okay";
+};
+
+&main_r5fss0 {
+       ti,cluster-mode = <0>;
+       status = "okay";
+};
+
+&main_r5fss0_core0 {
+       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+       memory-region = <&main_r5fss0_core0_dma_memory_region>,
+                       <&main_r5fss0_core0_memory_region>;
+       status = "okay";
+};
+
+&main_r5fss0_core1 {
+       mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+       memory-region = <&main_r5fss0_core1_dma_memory_region>,
+                       <&main_r5fss0_core1_memory_region>;
+       status = "okay";
+};