clk: renesas: r8a779a0: Add RAVB clocks

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210121100619.5653-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 613f7b499cfceee3522710d510042285dcfa6aea..f23fe9d5e5e1c7a3c444a40e91ee5d747b7ca07e 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -156,6 +156,12 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
+       DEF_MOD("avb0",         211,    R8A779A0_CLK_S3D2),
+       DEF_MOD("avb1",         212,    R8A779A0_CLK_S3D2),
+       DEF_MOD("avb2",         213,    R8A779A0_CLK_S3D2),
+       DEF_MOD("avb3",         214,    R8A779A0_CLK_S3D2),
+       DEF_MOD("avb4",         215,    R8A779A0_CLK_S3D2),
+       DEF_MOD("avb5",         216,    R8A779A0_CLK_S3D2),
        DEF_MOD("csi40",        331,    R8A779A0_CLK_CSI0),
        DEF_MOD("csi41",        400,    R8A779A0_CLK_CSI0),
        DEF_MOD("csi42",        401,    R8A779A0_CLK_CSI0),