arm64: dts: qcom: sm8650: Fix UFS PHY clocks

[ Upstream commit 0f9b8054bb4abd7b4686cc66b85f71fec9160136 ]

QMP PHY used in SM8650 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from TCSR

Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-17-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 2df77123a8c7bbef5efa6c1e2cc8ea8ef856cece..bad0eb84549fe5fd173803fe8a212fb80c3d7016 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2448,10 +2448,12 @@
                        compatible = "qcom,sm8650-qmp-ufs-phy";
                        reg = <0 0x01d80000 0 0x2000>;
 
-                       clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
-                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+                                <&tcsr TCSR_UFS_CLKREF_EN>;
                        clock-names = "ref",
-                                     "ref_aux";
+                                     "ref_aux",
+                                     "qref";
 
                        resets = <&ufs_mem_hc 0>;
                        reset-names = "ufsphy";