]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915/dsc: Add helper to enable the DSC configuration for a CRTC
authorImre Deak <imre.deak@intel.com>
Wed, 15 Oct 2025 16:19:28 +0000 (19:19 +0300)
committerImre Deak <imre.deak@intel.com>
Fri, 17 Oct 2025 18:48:00 +0000 (21:48 +0300)
Add a helper to enable the DSC compression configuration for a CRTC.
Follow-up changes will introduce tracking for the same DSC state on the
whole link, which will need to be set whenever DSC is enabled for the
CRTC. Also, according to the above, when querying the DSC state on the
link, both the CRTC's and the link's DSC state must be considered.

Setting the DSC configuration for a CRTC and querying the DSC
configuration for the link (added by follow-up changes) is better done
via helper functions based on the above, prepare for that here.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20251015161934.262108-2-imre.deak@intel.com
drivers/gpu/drm/i915/display/icl_dsi.c
drivers/gpu/drm/i915/display/intel_dp.c
drivers/gpu/drm/i915/display/intel_vdsc.c
drivers/gpu/drm/i915/display/intel_vdsc.h

index 37faa8f19f6e48821cea79c5585d9eea2415a42f..297368ff42a5eca9467aea283fa26e977d682142 100644 (file)
@@ -1655,7 +1655,7 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
        if (ret)
                return ret;
 
-       crtc_state->dsc.compression_enable = true;
+       intel_dsc_enable_on_crtc(crtc_state);
 
        return 0;
 }
index 7059d55687cf75afd63a635745ad1dd6f188a4ec..fc1949e0c4de680cfa4fd501aa36e7cd4e1d02a5 100644 (file)
@@ -2475,7 +2475,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
                return ret;
        }
 
-       pipe_config->dsc.compression_enable = true;
+       intel_dsc_enable_on_crtc(pipe_config);
+
        drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "
                    "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
                    pipe_config->pipe_bpp,
index bca747e24a7fa322caa500f37ae3cb55a2d7f7c1..803f3b395c79b7e4e91f1bb0e5daadbb947aecc2 100644 (file)
@@ -372,6 +372,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
        return 0;
 }
 
+void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state)
+{
+       crtc_state->dsc.compression_enable = true;
+}
+
 enum intel_display_power_domain
 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 {
index 2139391ff881d94f0a7c13d4308e058e04506a3a..8c7c7fb652c31024bef6080a3a55a9166fad2cfb 100644 (file)
@@ -20,6 +20,7 @@ void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
 void intel_dsc_enable(const struct intel_crtc_state *crtc_state);
 void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config);
+void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state);
 void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
 enum intel_display_power_domain
 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder);