{
u32 val;
+ cdclk_config->vco = vlv_get_hpll_vco(display->drm);
+
vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
- cdclk_config->vco = vlv_get_hpll_vco(display->drm);
cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk",
CCK_DISPLAY_CLOCK_CONTROL,
cdclk_config->vco);
{
int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
+ vlv_cck_get(drm);
+
/* Obtain SKU information */
hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) &
CCK_FUSE_HPLL_FREQ_MASK;
+ vlv_cck_put(drm);
+
return vco_freq[hpll_freq] * 1000;
}
struct drm_i915_private *dev_priv = to_i915(drm);
int hpll;
- vlv_cck_get(drm);
-
if (dev_priv->hpll_freq == 0)
dev_priv->hpll_freq = vlv_get_hpll_vco(drm);
+ vlv_cck_get(drm);
+
hpll = vlv_get_cck_clock(drm, name, reg, dev_priv->hpll_freq);
vlv_cck_put(drm);