iio: adc: ad7768-1: Ensure SYNC_IN pulse minimum timing requirement

[ Upstream commit 7e54d932873d91a55d1b89b7389876d78aeeab32 ]

The SYNC_IN pulse width must be at least 1.5 x Tmclk, corresponding to
~2.5 µs at the lowest supported MCLK frequency. Add a 3 µs delay to
ensure reliable synchronization timing even for the worst-case scenario.

Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
Reviewed-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/d3ee92a533cd1207cf5c5cc4d7bdbb5c6c267f68.1749063024.git.Jonathan.Santos@analog.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c
index 9580a7f7f73d28aea453e78b2dfff678328a3d73..883399ad80e03d1fbbc972d9026669e516b5965d 100644 (file)
--- a/drivers/iio/adc/ad7768-1.c
+++ b/drivers/iio/adc/ad7768-1.c
@@ -202,6 +202,24 @@ static int ad7768_spi_reg_write(struct ad7768_state *st,
        return spi_write(st->spi, st->data.d8, 2);
 }
 
+static int ad7768_send_sync_pulse(struct ad7768_state *st)
+{
+       /*
+        * The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk,
+        * where Tmclk is the MCLK period. The supported MCLK frequencies range
+        * from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse
+        * width of approximately 2.5 µs in the worst-case scenario (0.6 MHz).
+        *
+        * Add a delay to ensure the pulse width is always sufficient to
+        * trigger synchronization.
+        */
+       gpiod_set_value_cansleep(st->gpio_sync_in, 1);
+       fsleep(3);
+       gpiod_set_value_cansleep(st->gpio_sync_in, 0);
+
+       return 0;
+}
+
 static int ad7768_set_mode(struct ad7768_state *st,
                           enum ad7768_conv_mode mode)
 {
@@ -287,10 +305,7 @@ static int ad7768_set_dig_fil(struct ad7768_state *st,
                return ret;
 
        /* A sync-in pulse is required every time the filter dec rate changes */
-       gpiod_set_value(st->gpio_sync_in, 1);
-       gpiod_set_value(st->gpio_sync_in, 0);
-
-       return 0;
+       return ad7768_send_sync_pulse(st);
 }
 
 static int ad7768_set_freq(struct ad7768_state *st,