.buswidth = 4,
};
+static struct qcom_icc_node qhs_sdc1 = {
+ .name = "qhs_sdc1",
+ .channels = 1,
+ .buswidth = 4,
+};
+
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
.channels = 1,
.name = "qsm_cfg",
.channels = 1,
.buswidth = 4,
- .num_links = 29,
+ .num_links = 30,
.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
&qhs_camera_cfg, &qhs_clk_ctl,
&qhs_crypto0_cfg, &qhs_display_cfg,
&qhs_mss_cfg, &qhs_pcie_0_cfg,
&qhs_prng, &qhs_qdss_cfg,
&qhs_qspi, &qhs_qup1,
- &qhs_qup2, &qhs_sdc2,
+ &qhs_qup2, &qhs_sdc1, &qhs_sdc2,
&qhs_tcsr, &qhs_tlmm,
&qhs_ufs_mem_cfg, &qhs_usb3_0,
&qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
.name = "CN0",
.enable_mask = BIT(0),
.keepalive = true,
- .num_nodes = 43,
+ .num_nodes = 44,
.nodes = { &qsm_cfg, &qhs_ahb2phy0,
&qhs_ahb2phy1, &qhs_camera_cfg,
&qhs_clk_ctl, &qhs_crypto0_cfg,
&qhs_i3c_ibi1_cfg, &qhs_imem_cfg,
&qhs_mss_cfg, &qhs_pcie_0_cfg,
&qhs_prng, &qhs_qdss_cfg,
- &qhs_qspi, &qhs_sdc2,
+ &qhs_qspi, &qhs_sdc1, &qhs_sdc2,
&qhs_tcsr, &qhs_tlmm,
&qhs_ufs_mem_cfg, &qhs_usb3_0,
&qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
[SLAVE_QSPI_0] = &qhs_qspi,
[SLAVE_QUP_1] = &qhs_qup1,
[SLAVE_QUP_2] = &qhs_qup2,
+ [SLAVE_SDCC_1] = &qhs_sdc1,
[SLAVE_SDCC_2] = &qhs_sdc2,
[SLAVE_TCSR] = &qhs_tcsr,
[SLAVE_TLMM] = &qhs_tlmm,