drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag macro

Define PHY_C20_IS_DP, so it can be used instead of the plain bit number.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20251015125446.3931198-3-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 0d83145eff41f79ef407cbb8b7c2f43cf95fa50f..9492661f1645ccd7634f969c7c53898414e444d1 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2700,8 +2700,8 @@ static void intel_c20_pll_program(struct intel_display *display,
        /* 5. For DP or 6. For HDMI */
        if (is_dp) {
                intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
-                             BIT(6) | PHY_C20_DP_RATE_MASK,
-                             BIT(6) | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)),
+                             PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK,
+                             PHY_C20_IS_DP | PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)),
                              MB_WRITE_COMMITTED);
        } else {
                intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 25ab8808e54859cfc6628aacc1f78aed2660e1ec..ad2f7fb3beaec13775971d24a55179df98a3336d 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -298,6 +298,7 @@
 #define PHY_C20_RD_DATA_L              0xC08
 #define PHY_C20_RD_DATA_H              0xC09
 #define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
+#define   PHY_C20_IS_DP                        REG_BIT8(6)
 #define   PHY_C20_DP_RATE_MASK         REG_GENMASK8(4, 1)
 #define   PHY_C20_DP_RATE(val)         REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)
 #define PHY_C20_VDR_HDMI_RATE          0xD01