ASoC: wm8940: Correct PLL rate rounding

[ Upstream commit d05afb53c683ef7ed1228b593c3360f4d3126c58 ]

Using a single value of 22500000 for both 48000Hz and 44100Hz audio
will sometimes result in returning wrong dividers due to rounding.
Update the code to use the actual value for both.

Fixes: 294833fc9eb4 ("ASoC: wm8940: Rewrite code to set proper clocks")
Reported-by: Ankur Tyagi <ankur.tyagi85@gmail.com>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Tested-by: Ankur Tyagi <ankur.tyagi85@gmail.com>
Link: https://patch.msgid.link/20250821082639.1301453-2-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
index 8a532f7d750c8b02adb4bebf189ab59d0f33ebcf..5e8ed8a2c270a4cbde4ad403dfdee9a311d8d65f 100644 (file)
--- a/sound/soc/codecs/wm8940.c
+++ b/sound/soc/codecs/wm8940.c
@@ -693,7 +693,12 @@ static int wm8940_update_clocks(struct snd_soc_dai *dai)
        f = wm8940_get_mclkdiv(priv->mclk, fs256, &mclkdiv);
        if (f != priv->mclk) {
                /* The PLL performs best around 90MHz */
-               fpll = wm8940_get_mclkdiv(22500000, fs256, &mclkdiv);
+               if (fs256 % 8000)
+                       f = 22579200;
+               else
+                       f = 24576000;
+
+               fpll = wm8940_get_mclkdiv(f, fs256, &mclkdiv);
        }
 
        wm8940_set_dai_pll(dai, 0, 0, priv->mclk, fpll);