arm64: dts: renesas: r9a08g045: Add I3C node

Add the I3C node to RZ/G3S SoC DTSI.

Signed-off-by: Quynh Nguyen <quynh.nguyen.xb@renesas.com>
[wsa: adapted to upstream driver, moved bus frequencies to board file]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250807151434.5241-7-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 0364f89776e6bd09600d3b4b228036be843a4707..16e6ac61441787790b70f35f81925ef2f3d24d85 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -272,6 +272,42 @@
                        };
                };
 
+               i3c: i3c@1005b000 {
+                       compatible = "renesas,r9a08g045-i3c";
+                       reg = <0 0x1005b000 0 0x1000>;
+                       clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
+                                <&cpg CPG_MOD R9A08G045_I3C_TCLK>;
+                       clock-names = "pclk", "tclk";
+                       interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "ierr", "terr", "abort", "resp",
+                                         "cmd", "ibi", "rx", "tx", "rcv",
+                                         "st", "sp", "tend", "nack", "al",
+                                         "tmo", "wu", "exit";
+                       resets = <&cpg R9A08G045_I3C_PRESETN>,
+                                <&cpg R9A08G045_I3C_TRESETN>;
+                       reset-names = "presetn", "tresetn";
+                       power-domains = <&cpg>;
+                       #address-cells = <3>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                vbattb: clock-controller@1005c000 {
                        compatible = "renesas,r9a08g045-vbattb";
                        reg = <0 0x1005c000 0 0x1000>;