arm64: dts: imx8mm-kontron: Add overlay for LTE extension board

This is an addon for the BL i.MX8MM that features an LTE
modem, a TPM module, some LEDs and a pushbutton.

Signed-off-by: Annette Kobou <annette.kobou@kontron.de>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index dcc520355c99e5c1aa56678bc077880644f26eb2..d00858cb14078129124623dc78aa9a48c186ce00 100644 (file)
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -373,8 +373,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep.
 dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb
 
 imx8mm-kontron-dl-dtbs                 := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo
+imx8mm-kontron-bl-lte-dtbs             := imx8mm-kontron-bl.dtb imx8mm-kontron-bl-lte.dtbo
 
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-lte.dtb
 
 imx8mm-venice-gw72xx-0x-imx219-dtbs    := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo
 imx8mm-venice-gw72xx-0x-rpidsi-dtbs    := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso
new file mode 100644 (file)
index 0000000..324004b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2025 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include "imx8mm-pinfunc.h"
+
+&{/} {
+       compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
+
+       gpio-keys {
+               compatible = "gpio-keys";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpio_keys>;
+
+               key-user {
+                       label = "user";
+                       linux,code = <BTN_0>;
+                       gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+               };
+       };
+
+       leds {
+               compatible = "gpio-leds";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpio_led_lte>;
+
+               lte-led1-b {
+                       label = "lte-led1-blue";
+                       color = <LED_COLOR_ID_BLUE>;
+                       gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+               };
+
+               lte-led1-g {
+                       label = "lte-led1-green";
+                       color = <LED_COLOR_ID_GREEN>;
+                       gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+               };
+
+               lte-led1-r {
+                       label = "lte-led1-red";
+                       color = <LED_COLOR_ID_RED>;
+                       gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
+               };
+
+               lte-led2-b {
+                       label = "lte-led2-blue";
+                       color = <LED_COLOR_ID_BLUE>;
+                       gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
+               };
+
+               lte-led2-g {
+                       label = "lte-led2-green";
+                       color = <LED_COLOR_ID_GREEN>;
+                       gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
+               };
+
+               lte-led2-r {
+                       label = "lte-led2-red";
+                       color = <LED_COLOR_ID_RED>;
+                       gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;
+               };
+       };
+};
+
+&ecspi3 {
+       status = "disabled";
+};
+
+&i2c2 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       clock-frequency = <400000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_i2c2>;
+       status = "okay";
+
+       tpm@2e {
+               compatible = "infineon,slb9673", "tcg,tpm-tis-i2c";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tpm>;
+               reg = <0x2e>;
+               interrupt-parent = <&gpio3>;
+               interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+       };
+};
+
+&gpio3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpio3>;
+       gpio-line-names = "", "", "", "",
+                         "", "", "", "",
+                         "", "", "VDD_IO_REF", "TPM_PIRQ#",
+                         "TPM_RESET# ", "", "", "",
+                         "", "LTE_LED1_B", "LTE_LED1_G", "",
+                         "";
+
+       vdd-io-ref-hog {
+               gpio-hog;
+               gpios = <10 GPIO_ACTIVE_HIGH>;
+               line-name = "VDD_IO_REF";
+               output-high;
+       };
+
+       tpm-reset-hog {
+               gpio-hog;
+               gpios = <12 GPIO_ACTIVE_LOW>;
+               line-name = "TPM_RESET#";
+               output-low;
+       };
+};
+
+&gpio4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_gpio4>;
+       gpio-line-names = "", "", "LTE_RESET", "",
+                         "", "", "", "",
+                         "", "", "", "LTE_PWRKEY",
+                         "", "", "", "",
+                         "", "", "", "",
+                         "LTE_PWR_EN";
+};
+
+&gpio5 {
+       gpio-line-names = "", "", "", "",
+                         "", "", "", "",
+                         "", "", "", "",
+                         "", "", "", "",
+                         "", "", "", "",
+                         "", "", "LTE_LED2_G", "LTE_LED1_R",
+                         "LTE_LED2_R", "LTE_LED2_B";
+};
+
+&iomuxc {
+       pinctrl_gpio3: gpio3grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10             0x19 /* VDD_IO_REF */
+               >;
+       };
+
+       pinctrl_gpio4: gpio4grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2                0x19 /* LTE_RESET */
+                       MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11                0x19 /* LTE_PWRKEY */
+                       MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20               0x19 /* LTE_PWR_EN */
+               >;
+       };
+
+       pinctrl_gpio_keys: gpiokeysgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12               0x19 /* Pushbutton */
+               >;
+       };
+
+       pinctrl_gpio_led_lte: gpioledltegrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17               0x19 /* LTE_LED1_B */
+                       MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18               0x19 /* LTE_LED1_G */
+                       MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23               0x19 /* LTE_LED1_R */
+                       MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25               0x19 /* LTE_LED2_B */
+                       MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22               0x19 /* LTE_LED2_G */
+                       MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24               0x19 /* LTE_LED2_R */
+               >;
+       };
+
+       pinctrl_i2c2: i2c2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL                  0x40000083 /* I2C_A_SCL */
+                       MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA                  0x40000083 /* I2C_A_SDA */
+               >;
+       };
+
+       pinctrl_tpm: tpmgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11             0x19 /* TPM_PIRQ# */
+                       MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12             0x39 /* TPM_RESET# */
+               >;
+       };
+};