]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: broadcom: rp1: add csi nodes
authorGregor Herburger <gregor.herburger@linutronix.de>
Thu, 26 Feb 2026 08:55:55 +0000 (09:55 +0100)
committerFlorian Fainelli <florian.fainelli@broadcom.com>
Mon, 16 Mar 2026 20:55:30 +0000 (13:55 -0700)
The RaspberryPi 5 has 2 PiSP Camera front end controller on the RP1
chipset.

Add the relevant nodes to the devicetree.

Signed-off-by: Gregor Herburger <gregor.herburger@linutronix.de>
Link: https://lore.kernel.org/r/20260226-raspi-dts-updates-v1-2-60832d20ff04@linutronix.de
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
arch/arm64/boot/dts/broadcom/rp1-common.dtsi

index 58179094e30e7e0eb6242de9edc460fd4a0b7685..16f5359395835f7a145aad75094d525e10dcd2ca 100644 (file)
@@ -133,6 +133,34 @@ pci_ep_bus: pci-ep-bus@1 {
                #size-cells = <0>;
        };
 
+       rp1_csi0: csi@40110000 {
+               compatible = "raspberrypi,rp1-cfe";
+               reg = <0x0 0x40110000  0x0 0x100>, // CSI2 DMA address
+                     <0x0 0x40114000  0x0 0x100>, // PHY/CSI Host address
+                     <0x0 0x40120000  0x0 0x100>, // MIPI CFG address
+                     <0x0 0x40124000  0x0 0x1000>; // PiSP FE address
+               interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>;
+               assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>;
+               assigned-clock-rates = <25000000>;
+
+               status = "disabled";
+       };
+
+       rp1_csi1: csi@40128000 {
+               compatible = "raspberrypi,rp1-cfe";
+               reg = <0x0 0x40128000  0x0 0x100>, // CSI2 DMA address
+                     <0x0 0x4012c000  0x0 0x100>, // PHY/CSI Host address
+                     <0x0 0x40138000  0x0 0x100>, // MIPI CFG address
+                     <0x0 0x4013c000  0x0 0x1000>; // PiSP FE address
+               interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>;
+               assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>;
+               assigned-clock-rates = <25000000>;
+
+               status = "disabled";
+       };
+
        rp1_usb0: usb@40200000 {
                compatible = "snps,dwc3";
                reg = <0x00 0x40200000  0x0 0x100000>;