KVM: x86/pmu: Move PMU_CAP_{FW_WRITES,LBR_FMT} into msr-index.h header

Move PMU_CAP_{FW_WRITES,LBR_FMT} into msr-index.h and rename them with
PERF_CAP prefix to keep consistent with other perf capabilities macros.

No functional change intended.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Mingwei Zhang <mizhang@google.com>
Tested-by: Xudong Hao <xudong.hao@intel.com>
Link: https://lore.kernel.org/r/20250806195706.1650976-24-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 20fa4a79df1378dd7bb1db8f6318c8dd465261e6..717baeba6db3c604e3a0c1fcb29b2448909ef8cb 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -315,12 +315,15 @@
 #define PERF_CAP_PT_IDX                        16
 
 #define MSR_PEBS_LD_LAT_THRESHOLD      0x000003f6
-#define PERF_CAP_PEBS_TRAP             BIT_ULL(6)
-#define PERF_CAP_ARCH_REG              BIT_ULL(7)
-#define PERF_CAP_PEBS_FORMAT           0xf00
-#define PERF_CAP_PEBS_BASELINE         BIT_ULL(14)
-#define PERF_CAP_PEBS_MASK     (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
-                                PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
+
+#define PERF_CAP_LBR_FMT               0x3f
+#define PERF_CAP_PEBS_TRAP             BIT_ULL(6)
+#define PERF_CAP_ARCH_REG              BIT_ULL(7)
+#define PERF_CAP_PEBS_FORMAT           0xf00
+#define PERF_CAP_FW_WRITES             BIT_ULL(13)
+#define PERF_CAP_PEBS_BASELINE         BIT_ULL(14)
+#define PERF_CAP_PEBS_MASK             (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
+                                        PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
 
 #define MSR_IA32_RTIT_CTL              0x00000570
 #define RTIT_CTL_TRACEEN               BIT(0)

diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h
index 5316c27f609995b7dcbd270108d27fc8659b06ff..f614428dbeda7d85a24aff245aad9ba745be8623 100644 (file)
--- a/arch/x86/kvm/vmx/capabilities.h
+++ b/arch/x86/kvm/vmx/capabilities.h
@@ -20,9 +20,6 @@ extern int __read_mostly pt_mode;
 #define PT_MODE_SYSTEM         0
 #define PT_MODE_HOST_GUEST     1
 
-#define PMU_CAP_FW_WRITES      (1ULL << 13)
-#define PMU_CAP_LBR_FMT                0x3f
-
 struct nested_vmx_msrs {
        /*
         * We only store the "true" versions of the VMX capability MSRs. We

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index b2a2c4ebf4487ca4654a34351050e74f9c027abf..343de013eacd5c65c720e9830abe0d18872012a6 100644 (file)
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -138,7 +138,7 @@ static inline u64 vcpu_get_perf_capabilities(struct kvm_vcpu *vcpu)
 
 static inline bool fw_writes_is_enabled(struct kvm_vcpu *vcpu)
 {
-       return (vcpu_get_perf_capabilities(vcpu) & PMU_CAP_FW_WRITES) != 0;
+       return (vcpu_get_perf_capabilities(vcpu) & PERF_CAP_FW_WRITES) != 0;
 }
 
 static inline struct kvm_pmc *get_fw_gp_pmc(struct kvm_pmu *pmu, u32 msr)
@@ -588,7 +588,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
 
        perf_capabilities = vcpu_get_perf_capabilities(vcpu);
        if (intel_pmu_lbr_is_compatible(vcpu) &&
-           (perf_capabilities & PMU_CAP_LBR_FMT))
+           (perf_capabilities & PERF_CAP_LBR_FMT))
                memcpy(&lbr_desc->records, &vmx_lbr_caps, sizeof(vmx_lbr_caps));
        else
                lbr_desc->records.nr = 0;

diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 75cd5768e8adb480a1f4b273150827b8be6a51ac..5d3a50547c3e39fd2bdfa70799d83d028ed7c42d 100644 (file)
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -2127,7 +2127,7 @@ u64 vmx_get_supported_debugctl(struct kvm_vcpu *vcpu, bool host_initiated)
            (host_initiated || guest_cpu_cap_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)))
                debugctl |= DEBUGCTLMSR_BUS_LOCK_DETECT;
 
-       if ((kvm_caps.supported_perf_cap & PMU_CAP_LBR_FMT) &&
+       if ((kvm_caps.supported_perf_cap & PERF_CAP_LBR_FMT) &&
            (host_initiated || intel_pmu_lbr_is_enabled(vcpu)))
                debugctl |= DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI;
 
@@ -2412,9 +2412,9 @@ int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                        vmx->pt_desc.guest.addr_a[index / 2] = data;
                break;
        case MSR_IA32_PERF_CAPABILITIES:
-               if (data & PMU_CAP_LBR_FMT) {
-                       if ((data & PMU_CAP_LBR_FMT) !=
-                           (kvm_caps.supported_perf_cap & PMU_CAP_LBR_FMT))
+               if (data & PERF_CAP_LBR_FMT) {
+                       if ((data & PERF_CAP_LBR_FMT) !=
+                           (kvm_caps.supported_perf_cap & PERF_CAP_LBR_FMT))
                                return 1;
                        if (!cpuid_model_is_consistent(vcpu))
                                return 1;
@@ -7810,7 +7810,7 @@ void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
 
 static __init u64 vmx_get_perf_capabilities(void)
 {
-       u64 perf_cap = PMU_CAP_FW_WRITES;
+       u64 perf_cap = PERF_CAP_FW_WRITES;
        u64 host_perf_cap = 0;
 
        if (!enable_pmu)
@@ -7830,7 +7830,7 @@ static __init u64 vmx_get_perf_capabilities(void)
                if (!vmx_lbr_caps.has_callstack)
                        memset(&vmx_lbr_caps, 0, sizeof(vmx_lbr_caps));
                else if (vmx_lbr_caps.nr)
-                       perf_cap |= host_perf_cap & PMU_CAP_LBR_FMT;
+                       perf_cap |= host_perf_cap & PERF_CAP_LBR_FMT;
        }
 
        if (vmx_pebs_supported()) {