zynqmp: DC5: Add support for XM019 DC5

Add initial support for zc1751 xm019 dc5
support. It has GEM1 and SD0 enabled.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index e36f2853a4e7efafe3d8adea716471922f0e8bc9..f47c7377e4c969b62d78386ae5236589c11c8ef6 100644 (file)
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -18,6 +18,9 @@ config TARGET_ZYNQMP_ZC1751_XM015_DC1
 config TARGET_ZYNQMP_ZC1751_XM016_DC2
        bool "ZynqMP ZC1751 XM016 DC2"
 
+config TARGET_ZYNQMP_ZC1751_XM019_DC5
+       bool "ZynqMP ZC1751 XM019 DC5"
+
 endchoice
 
 config SYS_BOARD
@@ -35,6 +38,7 @@ config SYS_CONFIG_NAME
        default "xilinx_zynqmp_zcu102" if TARGET_ZYNQMP_ZCU102
        default "xilinx_zynqmp_zc1751_xm015_dc1" if TARGET_ZYNQMP_ZC1751_XM015_DC1
        default "xilinx_zynqmp_zc1751_xm016_dc2" if TARGET_ZYNQMP_ZC1751_XM016_DC2
+       default "xilinx_zynqmp_zc1751_xm019_dc5" if TARGET_ZYNQMP_ZC1751_XM019_DC5
 
 config SECURE_IOU
        bool "Configure ZynqMP secure IOU"

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 952f459e973f89d523ff4455167df6a7552fe1ab..61348d30276fddb722a50e99d3352d9245fb9d70 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -58,7 +58,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb  \
        zynqmp-zcu102.dtb                       \
        zynqmp-zc1751-xm015-dc1.dtb             \
-       zynqmp-zc1751-xm016-dc2.dtb
+       zynqmp-zc1751-xm016-dc2.dtb             \
+       zynqmp-zc1751-xm019-dc5.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=                          \

diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
new file mode 100644 (file)
index 0000000..d9ef266
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -0,0 +1,120 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm019-dc5
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "zynqmp.dtsi"
+/include/ "zynqmp-clk.dtsi"
+/ {
+       model = "ZynqMP zc1751-xm019-dc5 RevA";
+       compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+       aliases {
+               ethernet0 = &gem1;
+               gpio0 = &gpio;
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               serial0 = &uart0;
+               serial1 = &uart1;
+       };
+
+       chosen {
+               bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
+               stdout-path = "serial0:115200n8";
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x0 0x80000000>, <0x8 0x00000000 0x80000000>;
+       };
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+       xlnx,overfetch; /* for testing purpose */
+       xlnx,ratectrl = <0>; /* for testing purpose */
+       xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+       status = "okay";
+       xlnx,ratectrl = <100>; /* for testing purpose */
+       xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+       status = "okay";
+};
+
+&fpd_dma_chan4 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+       status = "okay";
+};
+
+&fpd_dma_chan6 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+       status = "okay";
+};
+
+&fpd_dma_chan8 {
+       status = "okay";
+       xlnx,include-sg; /* for testing purpose */
+};
+
+&gem1 {
+       status = "okay";
+       local-mac-address = [00 0a 35 00 02 90];
+       phy-handle = <&phy0>;
+       phy-mode = "rgmii-id";
+       phy0: phy@0 {
+               reg = <0>;
+       };
+};
+
+&gpio {
+       status = "okay";
+};
+
+/* FIXME: Add device */
+&i2c0 {
+       status = "okay";
+};
+
+/* FIXME: Add device */
+&i2c1 {
+       status = "okay";
+};
+
+&sdhci0 {
+       status = "okay";
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&watchdog0 {
+       status = "okay";
+};

diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS
index 756e4d69d630678ce6cdad004efbac881ff0f95b..9066ba0b16a869a25516d9cb56340bdb3808d38c 100644 (file)
--- a/board/xilinx/zynqmp/MAINTAINERS
+++ b/board/xilinx/zynqmp/MAINTAINERS
@@ -7,9 +7,11 @@ F:     include/configs/xilinx_zynqmp_ep.h
 F:     include/configs/xilinx_zynqmp_mini.h
 F:     include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
 F:     include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
+F:     include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
 F:     include/configs/xilinx_zynqmp_zcu102.h
 F:     configs/xilinx_zynqmp_ep_defconfig
 F:     configs/xilinx_zynqmp_mini_qspi_defconfig
 F:     configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
 F:     configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+F:     configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
 F:     configs/xilinx_zynqmp_zcu102_defconfig

diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
new file mode 100644 (file)
index 0000000..958d9b0
--- /dev/null
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_TARGET_ZYNQMP_ZC1751_XM019_DC5=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_OF_EMBED=y

diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
new file mode 100644 (file)
index 0000000..d74137e
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
@@ -0,0 +1,39 @@
+/*
+ * Configuration for Xilinx ZynqMP zc1751 XM019 DC5
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
+#define __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H
+
+#define CONFIG_ZYNQ_GEM1
+#define CONFIG_ZYNQ_GEM_PHY_ADDR1      -1
+
+#define CONFIG_ZYNQ_SERIAL_UART0
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_ZYNQ
+
+#define CONFIG_IDENT_STRING    " Xilinx ZynqMP ZC1751 xm019 dc5"
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_SDRAM_BASE          0
+#define CONFIG_SYS_SDRAM_SIZE          0x80000000
+
+#define CONFIG_KERNEL_FDT_OFST_SIZE \
+       "kernel_offset=0x400000\0" \
+       "fdt_offset=0x2400000\0" \
+       "kernel_size=0x2000000\0" \
+       "fdt_size=0x80000\0"
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */