rs6000.md: Enable patterns using rlwinm for PowerPC64.

	* config/rs6000/rs6000.md: Enable patterns using rlwinm for
	PowerPC64.  Replace "T" and "S" constraints with "n" when the
	predicate will do.  Formatting fixes.
	(extzvsi_internal2): Use "andi.", "andis." and attr type of "compare"
	as for extzvsi_internal1.

From-SVN: r55770

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ada205d533b0033269d1f12d4bfa1384714ec6dd..da23465410f65aaaa8750e09cfdda817ccdc3c18 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2002-07-26  Alan Modra  <amodra@bigpond.net.au>
+
+       * config/rs6000/rs6000.md: Enable patterns using rlwinm for
+       PowerPC64.  Replace "T" and "S" constraints with "n" when the
+       predicate will do.  Formatting fixes.
+       (extzvsi_internal2): Use "andi.", "andis." and attr type of "compare"
+       as for extzvsi_internal1.
+
 2002-07-25  Neil Booth  <neil@daikokuya.co.uk>
 
        * dwarfout.c (VERSION_ASM_OP, DERIV_BEGIN_LABEL_FMT,

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 52c86079cb6d3f0158577e11784640f48b026787..bfa04ab2a842561df3b3ab6e4482b975475a2771 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3811,7 +3811,7 @@
                         (match_operand:SI 3 "const_int_operand" "i,i"))
                    (const_int 0)))
    (clobber (match_scratch:SI 4 "=r,r"))]
-  "! TARGET_POWERPC64"
+  ""
   "*
 {
   int start = INTVAL (operands[3]) & 31;
@@ -3853,7 +3853,7 @@
                         (match_operand:SI 3 "const_int_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:SI 4 ""))]
-  "! TARGET_POWERPC64 && reload_completed"
+  "reload_completed"
   [(set (match_dup 4)
        (zero_extract:SI (match_dup 1) (match_dup 2)
                         (match_dup 3)))
@@ -3870,7 +3870,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
-  "! TARGET_POWERPC64"
+  ""
   "*
 {
   int start = INTVAL (operands[3]) & 31;
@@ -3880,10 +3880,14 @@
   if (which_alternative == 1)
      return \"#\";
 
-  if (start >= 16 && start + size == 32)
+  if ((start > 0 && start + size <= 16) || start >= 16)
     {
-      operands[3] = GEN_INT ((1 << (32 - start)) - 1);
-      return \"{andil.|andi.} %0,%1,%3\";
+      operands[3] = GEN_INT (((1 << (16 - (start & 15)))
+                             - (1 << (16 - (start & 15) - size))));
+      if (start < 16)
+       return \"{andiu.|andis.} %0,%1,%3\";
+      else
+       return \"{andil.|andi.} %0,%1,%3\";
     }
 
   if (start + size >= 32)
@@ -3892,7 +3896,7 @@
     operands[3] = GEN_INT (start + size);
   return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
 }"
-  [(set_attr "type" "delayed_compare")
+  [(set_attr "type" "compare")
    (set_attr "length" "4,8")])
 
 (define_split
@@ -3903,7 +3907,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
        (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
-  "! TARGET_POWERPC64 && reload_completed"
+  "reload_completed"
   [(set (match_dup 0)
        (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
    (set (match_dup 4)
@@ -3986,7 +3990,7 @@
                               (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r"))]
-  "! TARGET_POWERPC64"
+  ""
   "@
    {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
    #"
@@ -3999,7 +4003,7 @@
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 ""))]
-  "! TARGET_POWERPC64 && reload_completed"
+  "reload_completed"
   [(set (match_dup 3)
        (rotate:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
@@ -4014,7 +4018,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (rotate:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWERPC64"
+  ""
   "@
    {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
    #"
@@ -4028,7 +4032,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
        (rotate:SI (match_dup 1) (match_dup 2)))]
-  "! TARGET_POWERPC64 && reload_completed"
+  "reload_completed"
   [(set (match_dup 0)
        (rotate:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 3)
@@ -4040,7 +4044,7 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                           (match_operand:SI 2 "reg_or_cint_operand" "ri"))
-               (match_operand:SI 3 "mask_operand" "T")))]
+               (match_operand:SI 3 "mask_operand" "n")))]
   ""
   "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
 
@@ -4049,10 +4053,10 @@
        (compare:CC (and:SI
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
                                (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-                    (match_operand:SI 3 "mask_operand" "T,T"))
+                    (match_operand:SI 3 "mask_operand" "n,n"))
                    (const_int 0)))
    (clobber (match_scratch:SI 4 "=r,r"))]
-  "! TARGET_POWERPC64"
+  ""
   "@
    {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
    #"
@@ -4067,7 +4071,7 @@
                     (match_operand:SI 3 "mask_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:SI 4 ""))]
-  "! TARGET_POWERPC64 && reload_completed"
+  "reload_completed"
   [(set (match_dup 4)
        (and:SI (rotate:SI (match_dup 1)
                                (match_dup 2))
@@ -4082,11 +4086,11 @@
        (compare:CC (and:SI
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
                                (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
-                    (match_operand:SI 3 "mask_operand" "T,T"))
+                    (match_operand:SI 3 "mask_operand" "n,n"))
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "! TARGET_POWERPC64"
+  ""
   "@
    {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
    #"
@@ -4102,7 +4106,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
        (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "! TARGET_POWERPC64 && reload_completed"
+  "reload_completed"
   [(set (match_dup 0)
        (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (set (match_dup 4)
@@ -4420,7 +4424,7 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                           (match_operand:SI 2 "const_int_operand" "i"))
-               (match_operand:SI 3 "mask_operand" "T")))]
+               (match_operand:SI 3 "mask_operand" "n")))]
   "includes_lshift_p (operands[2], operands[3])"
   "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
 
@@ -4429,10 +4433,10 @@
        (compare:CC
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
                            (match_operand:SI 2 "const_int_operand" "i,i"))
-                (match_operand:SI 3 "mask_operand" "T,T"))
+                (match_operand:SI 3 "mask_operand" "n,n"))
         (const_int 0)))
    (clobber (match_scratch:SI 4 "=r,r"))]
-  "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
+  "includes_lshift_p (operands[2], operands[3])"
   "@
    {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
    #"
@@ -4447,7 +4451,7 @@
                 (match_operand:SI 3 "mask_operand" ""))
         (const_int 0)))
    (clobber (match_scratch:SI 4 ""))]
-  "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
+  "includes_lshift_p (operands[2], operands[3]) && reload_completed"
   [(set (match_dup 4)
        (and:SI (ashift:SI (match_dup 1) (match_dup 2))
                 (match_dup 3)))
@@ -4461,11 +4465,11 @@
        (compare:CC
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
                            (match_operand:SI 2 "const_int_operand" "i,i"))
-                (match_operand:SI 3 "mask_operand" "T,T"))
+                (match_operand:SI 3 "mask_operand" "n,n"))
         (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
+  "includes_lshift_p (operands[2], operands[3])"
   "@
    {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
    #"
@@ -4481,7 +4485,7 @@
         (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
        (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
+  "includes_lshift_p (operands[2], operands[3]) && reload_completed"
   [(set (match_dup 0)
        (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (set (match_dup 4)
@@ -4659,7 +4663,7 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
        (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                             (match_operand:SI 2 "const_int_operand" "i"))
-               (match_operand:SI 3 "mask_operand" "T")))]
+               (match_operand:SI 3 "mask_operand" "n")))]
   "includes_rshift_p (operands[2], operands[3])"
   "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
 
@@ -4668,10 +4672,10 @@
        (compare:CC
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
                              (match_operand:SI 2 "const_int_operand" "i,i"))
-                (match_operand:SI 3 "mask_operand" "T,T"))
+                (match_operand:SI 3 "mask_operand" "n,n"))
         (const_int 0)))
    (clobber (match_scratch:SI 4 "=r,r"))]
-  "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
+  "includes_rshift_p (operands[2], operands[3])"
   "@
    {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
    #"
@@ -4686,7 +4690,7 @@
                 (match_operand:SI 3 "mask_operand" ""))
         (const_int 0)))
    (clobber (match_scratch:SI 4 ""))]
-  "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
+  "includes_rshift_p (operands[2], operands[3]) && reload_completed"
   [(set (match_dup 4)
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
                 (match_dup 3)))
@@ -4700,11 +4704,11 @@
        (compare:CC
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
                              (match_operand:SI 2 "const_int_operand" "i,i"))
-                (match_operand:SI 3 "mask_operand" "T,T"))
+                (match_operand:SI 3 "mask_operand" "n,n"))
         (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
+  "includes_rshift_p (operands[2], operands[3])"
   "@
    {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
    #"
@@ -4720,7 +4724,7 @@
         (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
-  "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
+  "includes_rshift_p (operands[2], operands[3]) && reload_completed"
   [(set (match_dup 0)
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (set (match_dup 4)
@@ -6834,7 +6838,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
        (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
                           (match_operand:DI 2 "reg_or_cint_operand" "ri"))
-               (match_operand:DI 3 "mask64_operand" "S")))]
+               (match_operand:DI 3 "mask64_operand" "n")))]
   "TARGET_POWERPC64"
   "rld%I2c%B3 %0,%1,%H2,%S3")
 
@@ -6843,7 +6847,7 @@
        (compare:CC (and:DI
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
                                (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
-                    (match_operand:DI 3 "mask64_operand" "S,S"))
+                    (match_operand:DI 3 "mask64_operand" "n,n"))
                    (const_int 0)))
    (clobber (match_scratch:DI 4 "=r,r"))]
   "TARGET_POWERPC64"
@@ -6876,7 +6880,7 @@
        (compare:CC (and:DI
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
                                (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
-                    (match_operand:DI 3 "mask64_operand" "S,S"))
+                    (match_operand:DI 3 "mask64_operand" "n,n"))
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
        (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -7291,7 +7295,7 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
        (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
                           (match_operand:SI 2 "const_int_operand" "i"))
-               (match_operand:DI 3 "mask64_operand" "S")))]
+               (match_operand:DI 3 "mask64_operand" "n")))]
   "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
   "rldicr %0,%1,%H2,%S3")
 
@@ -7300,7 +7304,7 @@
        (compare:CC
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
                            (match_operand:SI 2 "const_int_operand" "i,i"))
-                (match_operand:DI 3 "mask64_operand" "S,S"))
+                (match_operand:DI 3 "mask64_operand" "n,n"))
         (const_int 0)))
    (clobber (match_scratch:DI 4 "=r,r"))]
   "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
@@ -7333,7 +7337,7 @@
        (compare:CC
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
                            (match_operand:SI 2 "const_int_operand" "i,i"))
-                   (match_operand:DI 3 "mask64_operand" "S,S"))
+                   (match_operand:DI 3 "mask64_operand" "n,n"))
         (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
        (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
@@ -11219,7 +11223,7 @@
    (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
        (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
                   (match_dup 3)))]
-  "! TARGET_POWERPC64"
+  ""
   "*
 {
   int is_bit = ccr_bit (operands[1], 1);
@@ -11254,7 +11258,7 @@
    (set (match_operand:SI 4 "gpc_reg_operand" "")
        (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
                   (match_dup 3)))]
-  "! TARGET_POWERPC64 && reload_completed"
+  "reload_completed"
   [(set (match_dup 4)
        (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
                   (match_dup 3)))
@@ -11620,9 +11624,9 @@
    (clobber (match_scratch:SI 4 ""))]
   "! TARGET_POWERPC64 && reload_completed"
   [(parallel [(set (match_dup 3)
-                  (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
-                                        (const_int 31))
-                           (match_dup 2)))
+                  (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
+                                        (const_int 31))
+                           (match_dup 2)))
               (clobber (match_dup 4))])
    (set (match_dup 0)
        (compare:CC (match_dup 3)
@@ -15105,7 +15109,6 @@
 (define_insn "altivec_vmrglb"
   [(set (match_operand:V16QI 0 "register_operand" "=v")
         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
-                                          
                                           (parallel [(const_int 0)
                                                      (const_int 1)
                                                      (const_int 2)