DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(PCIE_DW_AMD)
-#define VERSAL2_MEM_MAP_USED 6
+#define VERSAL2_MEM_MAP_USED 4
#else
-#define VERSAL2_MEM_MAP_USED 5
+#define VERSAL2_MEM_MAP_USED 3
#endif
#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- .virt = 0x600000000UL,
- .phys = 0x600000000UL,
- .size = 0x800000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0xe00000000UL,
- .phys = 0xe00000000UL,
- .size = 0xf200000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
#if CONFIG_IS_ENABLED(PCIE_DW_AMD)
}, {
/* PCIe DBI (1 MB) and config space (255 MB) are contiguous */