spi: zynq_qspi: Remove hardcoded frequencies

Remove hardcoded frequencies in favor of using the zyng clock framework.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index dee246e789c7e20a4a9e455f57236c5a81b4ef7e..dd8a6aa741b830b04cded11328d40c8b347a38e2 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -159,12 +159,6 @@ out:
        zynq_slcr_lock();
 }
 
-u32 zynq_slcr_get_lqspi_clk_ctrl(void)
-{
-       /* Get the lqspi_clkk_ctrl register value */
-       return readl(&slcr_base->lqspi_clk_ctrl);
-}
-
 void zynq_slcr_devcfg_disable(void)
 {
        zynq_slcr_unlock();

diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 6bf274a40ad7889f1b1d4e1db0328a6d7f7b48fa..f0202c3694e6eab410c8c565883363da4d31d9b8 100644 (file)
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -15,7 +15,6 @@ extern void zynq_slcr_cpu_reset(void);
 extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
 extern void zynq_slcr_devcfg_disable(void);
 extern void zynq_slcr_devcfg_enable(void);
-extern u32 zynq_slcr_get_lqspi_clk_ctrl(void);
 extern u32 zynq_slcr_get_boot_mode(void);
 extern u32 zynq_slcr_get_idcode(void);
 extern int zynq_slcr_get_mio_pin_status(const char *periph);

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 89f028e168f3b32dbecfdc5009afdd883d4500ee..bb207a5ded62f5b36473515307a9d5365f71cdc3 100644 (file)
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -14,6 +14,7 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/clk.h>
 
 /* QSPI Transmit Data Register */
 #define ZYNQ_QSPI_TXD_00_00_OFFSET     0x1C /* Transmit 4-byte inst, WO */
@@ -869,7 +870,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
                unsigned int max_hz, unsigned int mode)
 {
        int is_dual;
-       unsigned long lqspi_clk_ctrl_reg;
        unsigned long lqspi_frequency;
        struct zynq_qspi_slave *qspi;
 
@@ -895,13 +895,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
                return NULL;
        }
 
-       /*
-        * Read the lqspi_clk_ctrl_reg register and calculate the frequency.
-        * If failure revert to 200Mhz
-        */
-       lqspi_clk_ctrl_reg = zynq_slcr_get_lqspi_clk_ctrl();
-       lqspi_frequency = (CONFIG_CPU_FREQ_HZ / ((lqspi_clk_ctrl_reg & 0x3F00)>>
-                               8));
+       lqspi_frequency = zynq_clk_get_rate(lqspi_clk);
        if (!lqspi_frequency) {
                debug("Defaulting to 200000000 Hz qspi clk");
                qspi->qspi.master.input_clk_hz = 200000000;
@@ -921,9 +915,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
        qspi->qspi.bits_per_word = 32;
        zynq_qspi_setup_transfer(&qspi->qspi, NULL);
 
-       debug("%s: lqspi_clk_ctrl_reg: %ld CONFIG_CPU_FREQ_HZ %d\n",
-             __func__, lqspi_clk_ctrl_reg, CONFIG_CPU_FREQ_HZ);
-
        return &qspi->slave;
 }