arm64: Provide dcache_inval_poc_nosync helper

dcache_inval_poc_nosync does not wait for the data cache invalidation to
complete. Later, we defer the synchronization so we can wait for all SG
entries together.

Cc: Leon Romanovsky <leon@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Ryan Roberts <ryan.roberts@arm.com>
Cc: Suren Baghdasaryan <surenb@google.com>
Cc: Tangquan Zheng <zhengtangquan@oppo.com>
Tested-by: Xueyuan Chen <xueyuan.chen21@gmail.com>
Signed-off-by: Barry Song <baohua@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20260228221258.59918-1-21cnbao@gmail.com

diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index 9b6d0a62cf3d007123fca54a1a4c5430d3d23244..382b4ac3734dcfcfcd7e1688ac5717dc55d48f7f 100644 (file)
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -74,6 +74,7 @@ extern void icache_inval_pou(unsigned long start, unsigned long end);
 extern void dcache_clean_inval_poc(unsigned long start, unsigned long end);
 extern void dcache_inval_poc(unsigned long start, unsigned long end);
 extern void dcache_clean_poc(unsigned long start, unsigned long end);
+extern void dcache_inval_poc_nosync(unsigned long start, unsigned long end);
 extern void dcache_clean_poc_nosync(unsigned long start, unsigned long end);
 extern void dcache_clean_pop(unsigned long start, unsigned long end);
 extern void dcache_clean_pou(unsigned long start, unsigned long end);

diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 4a7c7e03785d174989fc6b9e9c2708f0c233a446..ab75c050f55909aa21d062487ac38abcd4b5e81b 100644 (file)
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -132,17 +132,7 @@ alternative_else_nop_endif
        ret
 SYM_FUNC_END(dcache_clean_pou)
 
-/*
- *     dcache_inval_poc(start, end)
- *
- *     Ensure that any D-cache lines for the interval [start, end)
- *     are invalidated. Any partial lines at the ends of the interval are
- *     also cleaned to PoC to prevent data loss.
- *
- *     - start   - kernel start address of region
- *     - end     - kernel end address of region
- */
-SYM_FUNC_START(__pi_dcache_inval_poc)
+.macro __dcache_inval_poc_nosync
        dcache_line_size x2, x3
        sub     x3, x2, #1
        tst     x1, x3                          // end cache line aligned?
@@ -158,11 +148,41 @@ SYM_FUNC_START(__pi_dcache_inval_poc)
 3:     add     x0, x0, x2
        cmp     x0, x1
        b.lo    2b
+.endm
+
+/*
+ *     dcache_inval_poc(start, end)
+ *
+ *     Ensure that any D-cache lines for the interval [start, end)
+ *     are invalidated. Any partial lines at the ends of the interval are
+ *     also cleaned to PoC to prevent data loss.
+ *
+ *     - start   - kernel start address of region
+ *     - end     - kernel end address of region
+ */
+SYM_FUNC_START(__pi_dcache_inval_poc)
+       __dcache_inval_poc_nosync
        dsb     sy
        ret
 SYM_FUNC_END(__pi_dcache_inval_poc)
 SYM_FUNC_ALIAS(dcache_inval_poc, __pi_dcache_inval_poc)
 
+/*
+ *     dcache_inval_poc_nosync(start, end)
+ *
+ *     Issue the instructions of D-cache lines for the interval [start, end)
+ *     for invalidation. Not necessarily cleaned to PoC till an explicit dsb
+ *     sy is issued later
+ *
+ *     - start   - kernel start address of region
+ *     - end     - kernel end address of region
+ */
+SYM_FUNC_START(__pi_dcache_inval_poc_nosync)
+       __dcache_inval_poc_nosync
+       ret
+SYM_FUNC_END(__pi_dcache_inval_poc_nosync)
+SYM_FUNC_ALIAS(dcache_inval_poc_nosync, __pi_dcache_inval_poc_nosync)
+
 /*
  *     dcache_clean_poc(start, end)
  *