]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers
authorSuraj Kandpal <suraj.kandpal@intel.com>
Sat, 1 Nov 2025 03:24:49 +0000 (08:54 +0530)
committerSuraj Kandpal <suraj.kandpal@intel.com>
Sat, 1 Nov 2025 03:33:39 +0000 (09:03 +0530)
Add LT Phy related VDR and pipe registers into its own new file.

Bspec: 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-2-suraj.kandpal@intel.com
drivers/gpu/drm/i915/display/intel_lt_phy_regs.h [new file with mode: 0644]

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
new file mode 100644 (file)
index 0000000..6eaa038
--- /dev/null
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_LT_PHY_REGS_H__
+#define __INTEL_LT_PHY_REGS_H__
+
+/* LT Phy Vendor Register */
+#define LT_PHY_VDR_0_CONFIG    0xC02
+#define  LT_PHY_VDR_DP_PLL_ENABLE      REG_BIT(7)
+#define LT_PHY_VDR_1_CONFIG    0xC03
+#define  LT_PHY_VDR_RATE_ENCODING_MASK REG_GENMASK8(6, 3)
+#define  LT_PHY_VDR_MODE_ENCODING_MASK REG_GENMASK8(2, 0)
+#define LT_PHY_VDR_2_CONFIG    0xCC3
+
+#define LT_PHY_VDR_X_ADDR_MSB(idx)     (0xC04 + 0x6 * (idx))
+#define LT_PHY_VDR_X_ADDR_LSB(idx)     (0xC05 + 0x6 * (idx))
+
+#define LT_PHY_VDR_X_DATAY(idx, y)     ((0xC06 + (3 - (y))) + 0x6 * (idx))
+
+#define LT_PHY_RATE_UPDATE             0xCC4
+
+#endif /* __INTEL_LT_PHY_REGS_H__ */