]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: imx8mm-kontron: Use the VSELECT signal to switch SD card IO voltage
authorFrieder Schrempf <frieder.schrempf@kontron.de>
Mon, 22 Aug 2022 08:03:50 +0000 (10:03 +0200)
committerSasha Levin <sashal@kernel.org>
Tue, 26 Mar 2024 22:21:17 +0000 (18:21 -0400)
[ Upstream commit eef2c0217e02b6c7ed5b10b82ea944127145e113 ]

It turns out that it is not necessary to declare the VSELECT signal as
GPIO and let the PMIC driver set it to a fixed high level. This switches
the voltage between 3.3V and 1.8V by setting the PMIC register for LDO5
accordingly.

Instead we can do it like other boards already do and simply mux the
VSELECT signal of the USDHC interface to the pin. This makes sure that
the correct voltage is selected by setting the PMIC's SD_VSEL input
to high or low accordingly.

Reported-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Heiko Thiery <heiko.thiery@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stable-dep-of: 008820524844 ("arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL board")
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi

index 25886622c8c405514592ff259d0a228c002e0894..00dff7c33310c70b3e3ee529d26c7d182f56fd8d 100644 (file)
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d0
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d0
                        MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
                >;
        };
 
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d4
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d4
                        MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
                >;
        };
 
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d6
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d6
                        MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
                >;
        };
 };
index 1b9fc3a926fcb969b2328183752f3f9761da0268..646615ca4b48ba0d3a49c01eeb7acf439582a30c 100644 (file)
@@ -86,7 +86,6 @@
                pinctrl-0 = <&pinctrl_pmic>;
                interrupt-parent = <&gpio1>;
                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-               sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 
                regulators {
                        reg_vdd_soc: BUCK1 {
        pinctrl_pmic: pmicgrp {
                fsl,pins = <
                        MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0               0x141
-                       MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4               0x141
                >;
        };