rs6000: Update existing mma insns to use wD constraint and update %A printer

This patch replaces the 'd' constraint that was used for accumulators
previously since they overlapped with the FPRs, to use 'wD' constraint
and the new accumulator_operand in the existing mma define_insns. The
behaviour without dense-math option will be same as before, only if
dense-math option is used will the DMR registers be used.

It also updates the %A operand printer to print the DMR register numbers
instead of FPR if dense-math option is enabled

2026-07-16  Avinash Jayakar  <avinashd@linux.ibm.com>
	    Vijay Shankar  <vijay@linux.ibm.com>

gcc/ChangeLog:
	* config/rs6000/mma.md (mma_xxsetaccz): Use wD constraint and
	accumulator operand.
	(mma_<vv>): Likewise.
	(mma_<avv>): Likewise.
	(mma_<pv>): Likewise.
	(mma_<apv>): Likewise.
	(mma_<vvi4i4i8>): Likewise.
	(mma_<avvi4i4i8>): Likewise.
	(mma_<vvi4i4i2>): Likewise.
	(mma_<avvi4i4i2>): Likewise.
	(mma_<vvi4i4>): Likewise.
	(mma_<avvi4i4>): Likewise.
	(mma_<pvi4i2>): Likewise.
	(mma_<apvi4i2>): Likewise.
	(mma_<vvi4i4i4>): Likewise.
	(mma_<avvi4i4i4>): Likewise.
	* config/rs6000/rs6000.cc (print_operand): Print DMR register
	numbers if dense math option enabled.

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 8d4a65a48b161732808b2002bc0ec43f6866fd2a..c40070abdcac31ce3dc5d73f21cfe72e71a1768d 100644 (file)
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -801,7 +801,7 @@
 ;; UNSPEC_VOLATILE.
 
 (define_insn "mma_xxsetaccz"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=wD")
        (unspec_volatile:XO [(const_int 0)]
                            UNSPECV_MMA_XXSETACCZ))]
   "TARGET_MMA"
@@ -816,7 +816,7 @@
   [(set_attr "type" "dmf")])
 
 (define_insn "mma_<vv>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
        (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
                    MMA_VV))]
@@ -825,8 +825,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<avv>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-       (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+       (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
                    MMA_AVV))]
@@ -835,7 +835,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<pv>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
        (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
                    MMA_PV))]
@@ -844,8 +844,8 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<apv>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-       (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+       (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
                    (match_operand:OO 2 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
                    MMA_APV))]
@@ -854,7 +854,7 @@
   [(set_attr "type" "mma")])
 
 (define_insn "mma_<vvi4i4i8>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
        (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
                    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -867,8 +867,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4i8>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-       (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+       (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
                    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -881,7 +881,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<vvi4i4i2>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
        (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
                    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -894,8 +894,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4i2>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-       (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+       (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
                    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -908,7 +908,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<vvi4i4>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
        (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
                    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -920,8 +920,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-       (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+       (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
                    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -933,7 +933,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<pvi4i2>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
        (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
                    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -945,8 +945,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<apvi4i2>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-       (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+       (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
                    (match_operand:OO 2 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
                    (match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -958,7 +958,7 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<vvi4i4i4>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
        (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
                    (match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -971,8 +971,8 @@
    (set_attr "prefixed" "yes")])
 
 (define_insn "mma_<avvi4i4i4>"
-  [(set (match_operand:XO 0 "fpr_reg_operand" "=&d,&d")
-       (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+  [(set (match_operand:XO 0 "accumulator_operand" "=&wD,&wD")
+       (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
                    (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
                    (match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
                    (match_operand:SI 4 "const_0_to_15_operand" "n,n")

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6ff877dac6c1af3e56e41ff9ca269f31b5f12ffc..c620d1a31e87ae3ffc2d2dddc15c8dbcfad9dc29 100644 (file)
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -14258,6 +14258,15 @@ print_operand (FILE *file, rtx x, int code)
         output_operand.  */
 
     case 'A':
+      /* Use dense math register if TARGET_DMF enabled.  */
+      if (TARGET_DMF)
+       {
+         if (!REG_P (x) || !DMR_REGNO_P (REGNO (x)))
+           output_operand_lossage ("invalid %%A value");
+         else
+           fprintf (file, "%d", REGNO (x) - FIRST_DMR_REGNO);
+         return;
+       }
       /* Write the MMA accumulator number associated with VSX register X.  */
       if (!REG_P (x) || !FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0)
        output_operand_lossage ("invalid %%A value");