These numbers can be reused.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
#define ZYNQ_DDRC_BASEADDR 0xF8006000
#define ZYNQ_EFUSE_BASEADDR 0xF800D000
+/* Bootmode setting values */
+#define BOOT_MODES_MASK 0x0000000F
+#define QSPI_MODE 0x00000001
+#define NOR_FLASH_MODE 0x00000002
+#define NAND_FLASH_MODE 0x00000004
+#define SD_MODE 0x00000005
+#define JTAG_MODE 0x00000000
+
/* Reflect slcr offsets */
struct slcr_regs {
u32 scl; /* 0x0 */
DECLARE_GLOBAL_DATA_PTR;
-/* Bootmode setting values */
-#define BOOT_MODES_MASK 0x0000000F
-#define QSPI_MODE 0x00000001
-#define NOR_FLASH_MODE 0x00000002
-#define NAND_FLASH_MODE 0x00000004
-#define SD_MODE 0x00000005
-#define JTAG_MODE 0x00000000
-
#ifdef CONFIG_FPGA
Xilinx_desc fpga;