static void mt7620_mac_init(struct mt7620_gsw *gsw)
{
+ u32 val;
+
/* Internal ethernet requires PCIe RC mode */
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1);
/* Set Port 6 as CPU Port */
mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
+ val = mtk_switch_r32(gsw, GSW_REG_GMACCR);
+ val &= ~((GMACCR_JMB_LEN_MASK << GMACCR_JMB_LEN_SHIFT) | GMACCR_MAX_RX_PKT_LEN_MASK);
+ /* Set 2k max frame size and set MAX_RX_PKT_LEN to jumbo mode */
+ val |= (2 << GMACCR_JMB_LEN_SHIFT) | GMACCR_MAX_RX_PKT_LEN_JUMBO;
+ mtk_switch_w32(gsw, val, GSW_REG_GMACCR);
+
/* Enable MIB stats */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
}
#define GSW_REG_MAC_P1_MCR 0x200
// Global MAC control register
-#define GSW_REG_GMACCR 0x30E0
+#define GSW_REG_GMACCR 0x3FE0 /* correct address per MT7620A datasheet */
+#define GMACCR_JMB_LEN_MASK 0x0F
+#define GMACCR_JMB_LEN_SHIFT 2
+// MAX_RX_PKT_LEN field (bits 0:1): 0=1518, 1=1536, 2=jumbo
+#define GMACCR_MAX_RX_PKT_LEN_MASK 0x3
+#define GMACCR_MAX_RX_PKT_LEN_JUMBO 0x2
#define SYSC_REG_CHIP_REV_ID 0x0c
#define SYSC_REG_CFG1 0x14
#include "mdio.h"
#include "ethtool.h"
+#if defined(CONFIG_SOC_MT7620)
+#define DMA_FWD_REG MT7620A_GDMA1_FWD_CFG
+#define MAX_RX_LENGTH 2048
+#else
+#define DMA_FWD_REG FE_GDMA1_FWD_CFG
#define MAX_RX_LENGTH 1536
+#endif
+
#define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
#define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
#define DMA_DUMMY_DESC 0xffffffff
{
u32 fwd_cfg;
- fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
+ fwd_cfg = fe_r32(DMA_FWD_REG);
/* disable jumbo frame */
if (priv->flags & FE_FLAG_JUMBO_FRAME)
/* set unicast/multicast/broadcast frame to cpu */
fwd_cfg &= ~0xffff;
- fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
+ fe_w32(fwd_cfg, DMA_FWD_REG);
}
static void fe_rxcsum_config(bool enable)
{
if (enable)
- fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
+ fe_w32(fe_r32(DMA_FWD_REG) | (FE_GDM1_ICS_EN |
FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
- FE_GDMA1_FWD_CFG);
+ DMA_FWD_REG);
else
- fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
+ fe_w32(fe_r32(DMA_FWD_REG) & ~(FE_GDM1_ICS_EN |
FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
- FE_GDMA1_FWD_CFG);
+ DMA_FWD_REG);
}
static void fe_txcsum_config(bool enable)
fe_stop(dev);
if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
- fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
+ fwd_cfg = fe_r32(DMA_FWD_REG);
if (new_mtu <= ETH_DATA_LEN) {
fwd_cfg &= ~FE_GDM1_JMB_EN;
} else {
fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
}
- fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
+ fe_w32(fwd_cfg, DMA_FWD_REG);
}
return fe_open(dev);
NETIF_F_HW_VLAN_CTAG_RX);
netdev->features |= netdev->hw_features;
- if (IS_ENABLED(CONFIG_SOC_MT7621))
+ if (IS_ENABLED(CONFIG_SOC_MT7620) || IS_ENABLED(CONFIG_SOC_MT7621))
netdev->max_mtu = 2048;
/* fake rx vlan filter func. to support tx vlan offload func */