drm/msm/dsi: use the correct VREG_CTRL_1 value for 4nm cphy

[ Upstream commit b3e0f94d15700ac8e8c1c2355834f5d5c753c41d ]

Use the same value as the downstream driver. This change is needed for CPHY
mode to work correctly.

Fixes: 8b034e677111 ("drm/msm/dsi: add support for DSI-PHY on SM8550")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/566987/
Link: https://lore.kernel.org/r/20231110000216.29979-1-jonathan@marek.ca
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 3b1ed02f644d2821221f54f4a46f611692a4c413..89a6344bc8653d61a3dea4860cb3320f1bcf7a15 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -918,7 +918,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
        if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
                if (phy->cphy_mode) {
                        vreg_ctrl_0 = 0x45;
-                       vreg_ctrl_1 = 0x45;
+                       vreg_ctrl_1 = 0x41;
                        glbl_rescode_top_ctrl = 0x00;
                        glbl_rescode_bot_ctrl = 0x00;
                } else {