Fixes for 6.0

Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/queue-6.0/clk-renesas-r8a779f0-add-sdh0-clock.patch b/queue-6.0/clk-renesas-r8a779f0-add-sdh0-clock.patch
new file mode 100644 (file)
index 0000000..9c242c5
--- /dev/null
+++ b/queue-6.0/clk-renesas-r8a779f0-add-sdh0-clock.patch
@@ -0,0 +1,37 @@
+From 3ef1aaa9bdf6568a8f91d24b257d33ffe819a94a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 11 Jul 2022 15:46:54 +0200
+Subject: clk: renesas: r8a779f0: Add SDH0 clock
+
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+[ Upstream commit 9b5dd1ff705c68549f7a2a91dd8beee14bc543e1 ]
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+Link: https://lore.kernel.org/r/20220711134656.277730-2-wsa+renesas@sang-engineering.com
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Stable-dep-of: 1e56ebc9872f ("clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks")
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/renesas/r8a779f0-cpg-mssr.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+index b7936f422c27..9bd6746e6a07 100644
+--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+@@ -108,7 +108,8 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
+       DEF_FIXED("cbfusa",     R8A779F0_CLK_CBFUSA,    CLK_EXTAL,      2, 1),
+       DEF_FIXED("cpex",       R8A779F0_CLK_CPEX,      CLK_EXTAL,      2, 1),
+ 
+-      DEF_GEN4_SD("sd0",      R8A779F0_CLK_SD0,       CLK_SDSRC,      0x870),
++      DEF_GEN4_SDH("sdh0",    R8A779F0_CLK_SD0H,      CLK_SDSRC,         0x870),
++      DEF_GEN4_SD("sd0",      R8A779F0_CLK_SD0,       R8A779F0_CLK_SD0H, 0x870),
+ 
+       DEF_BASE("rpc",         R8A779F0_CLK_RPC,       CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
+       DEF_BASE("rpcd2",       R8A779F0_CLK_RPCD2,     CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
+-- 
+2.35.1
+

diff --git a/queue-6.0/clk-renesas-r8a779f0-add-tmu-and-parent-sasync-clock.patch b/queue-6.0/clk-renesas-r8a779f0-add-tmu-and-parent-sasync-clock.patch
new file mode 100644 (file)
index 0000000..6032835
--- /dev/null
+++ b/queue-6.0/clk-renesas-r8a779f0-add-tmu-and-parent-sasync-clock.patch
@@ -0,0 +1,48 @@
+From f2027ee6aae5609b9d911e186242b1a2fb776197 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 26 Jul 2022 23:01:08 +0200
+Subject: clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks
+
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+[ Upstream commit 1e56ebc9872feb2cf9a002c0a23d79a68f6493cb ]
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Link: https://lore.kernel.org/r/20220726210110.1444-2-wsa+renesas@sang-engineering.com
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/clk/renesas/r8a779f0-cpg-mssr.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+index 9bd6746e6a07..738f71556621 100644
+--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
++++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+@@ -108,6 +108,11 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
+       DEF_FIXED("cbfusa",     R8A779F0_CLK_CBFUSA,    CLK_EXTAL,      2, 1),
+       DEF_FIXED("cpex",       R8A779F0_CLK_CPEX,      CLK_EXTAL,      2, 1),
+ 
++      DEF_FIXED("sasyncrt",   R8A779F0_CLK_SASYNCRT,  CLK_PLL5_DIV4,  48, 1),
++      DEF_FIXED("sasyncperd1", R8A779F0_CLK_SASYNCPERD1, CLK_PLL5_DIV4, 3, 1),
++      DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1),
++      DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1),
++
+       DEF_GEN4_SDH("sdh0",    R8A779F0_CLK_SD0H,      CLK_SDSRC,         0x870),
+       DEF_GEN4_SD("sd0",      R8A779F0_CLK_SD0,       R8A779F0_CLK_SD0H, 0x870),
+ 
+@@ -140,6 +145,11 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
+       DEF_MOD("sdhi0",        706,    R8A779F0_CLK_SD0),
+       DEF_MOD("sys-dmac0",    709,    R8A779F0_CLK_S0D3_PER),
+       DEF_MOD("sys-dmac1",    710,    R8A779F0_CLK_S0D3_PER),
++      DEF_MOD("tmu0",         713,    R8A779F0_CLK_SASYNCRT),
++      DEF_MOD("tmu1",         714,    R8A779F0_CLK_SASYNCPERD2),
++      DEF_MOD("tmu2",         715,    R8A779F0_CLK_SASYNCPERD2),
++      DEF_MOD("tmu3",         716,    R8A779F0_CLK_SASYNCPERD2),
++      DEF_MOD("tmu4",         717,    R8A779F0_CLK_SASYNCPERD2),
+       DEF_MOD("wdt",          907,    R8A779F0_CLK_R),
+       DEF_MOD("pfc0",         915,    R8A779F0_CLK_CL16M),
+       DEF_MOD("tsc",          919,    R8A779F0_CLK_CL16M),
+-- 
+2.35.1
+

diff --git a/queue-6.0/hwmon-jc42-fix-missing-unlock-on-error-in-jc42_write.patch b/queue-6.0/hwmon-jc42-fix-missing-unlock-on-error-in-jc42_write.patch
new file mode 100644 (file)
index 0000000..9820be0
--- /dev/null
+++ b/queue-6.0/hwmon-jc42-fix-missing-unlock-on-error-in-jc42_write.patch
@@ -0,0 +1,40 @@
+From b7024e66429bb0f1c8f5aceec87b4ff2bd430b95 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 27 Oct 2022 14:29:31 +0800
+Subject: hwmon: (jc42) Fix missing unlock on error in jc42_write()
+
+From: Yang Yingliang <yangyingliang@huawei.com>
+
+[ Upstream commit b744db17abf6a2efc2bfa80870cc88e9799a8ccc ]
+
+Add the missing unlock before return from function jc42_write()
+in the error handling case.
+
+Fixes: 37dedaee8bc6 ("hwmon: (jc42) Convert register access and caching to regmap/regcache")
+Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
+Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Link: https://lore.kernel.org/r/20221027062931.598247-1-yangyingliang@huawei.com
+Reported-by: kernel test robot <lkp@intel.com>
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/hwmon/jc42.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/hwmon/jc42.c b/drivers/hwmon/jc42.c
+index 5004b17c5682..50aea882ac09 100644
+--- a/drivers/hwmon/jc42.c
++++ b/drivers/hwmon/jc42.c
+@@ -350,7 +350,7 @@ static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
+               ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
+                                 &regval);
+               if (ret)
+-                      return ret;
++                      break;
+ 
+               /*
+                * JC42.4 compliant chips only support four hysteresis values.
+-- 
+2.35.1
+

diff --git a/queue-6.0/series b/queue-6.0/series
index 6534dd611f9fe2f69dacc04e06444c64744b7779..828319ded2385327f3b4b197074bee6a4e883c4e 100644 (file)
--- a/queue-6.0/series
+++ b/queue-6.0/series
@@ -993,3 +993,6 @@ scsi-target-iscsi-fix-a-race-condition-between-login.patch
 orangefs-fix-kmemleak-in-orangefs_prepare_debugfs_he.patch
 orangefs-fix-kmemleak-in-orangefs_sysfs_init.patch
 orangefs-fix-kmemleak-in-orangefs_-kernel-client-_de.patch
+clk-renesas-r8a779f0-add-sdh0-clock.patch
+clk-renesas-r8a779f0-add-tmu-and-parent-sasync-clock.patch
+hwmon-jc42-fix-missing-unlock-on-error-in-jc42_write.patch