]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
net: stmmac: remove dwmac4 DMA_CHAN_INTR_DEFAULT_[TR]X*
authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Fri, 27 Feb 2026 09:53:34 +0000 (09:53 +0000)
committerJakub Kicinski <kuba@kernel.org>
Tue, 3 Mar 2026 02:35:05 +0000 (18:35 -0800)
Remove the DMA_CHAN_INTR_DEFAULT_[TR]X* definitions, which are aliases
of their respective DMA_CHAN_INTR_ENA_[TR]IE definitions.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vvuXO-0000000Avn3-1hhD@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c

index 9d9077a4ac9f1fe1c8802968a30bddcf73f65d31..7fbd02a8119f10218514d44a49521c26d892977f 100644 (file)
@@ -111,8 +111,6 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
 /* DMA default interrupt mask for 4.00 */
 #define DMA_CHAN_INTR_DEFAULT_MASK     (DMA_CHAN_INTR_NORMAL | \
                                         DMA_CHAN_INTR_ABNORMAL)
-#define DMA_CHAN_INTR_DEFAULT_RX       (DMA_CHAN_INTR_ENA_RIE)
-#define DMA_CHAN_INTR_DEFAULT_TX       (DMA_CHAN_INTR_ENA_TIE)
 
 #define DMA_CHAN_INTR_NORMAL_4_10      (DMA_CHAN_INTR_ENA_NIE_4_10 | \
                                         DMA_CHAN_INTR_ENA_RIE | \
@@ -123,8 +121,6 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
 /* DMA default interrupt mask for 4.10a */
 #define DMA_CHAN_INTR_DEFAULT_MASK_4_10        (DMA_CHAN_INTR_NORMAL_4_10 | \
                                         DMA_CHAN_INTR_ABNORMAL_4_10)
-#define DMA_CHAN_INTR_DEFAULT_RX_4_10  (DMA_CHAN_INTR_ENA_RIE)
-#define DMA_CHAN_INTR_DEFAULT_TX_4_10  (DMA_CHAN_INTR_ENA_TIE)
 
 #define DMA_CHAN_RX_WATCHDOG(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x38)
 #define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x)    (dma_chanx_base_addr(addrs, x) + 0x3c)
index c098047a3bff8ab29987dde34764c15770cdba60..9217308bfd38545e67716e41542dad21ff9871e5 100644 (file)
@@ -116,9 +116,9 @@ void dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
        u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
 
        if (rx)
-               value |= DMA_CHAN_INTR_DEFAULT_RX;
+               value |= DMA_CHAN_INTR_ENA_RIE;
        if (tx)
-               value |= DMA_CHAN_INTR_DEFAULT_TX;
+               value |= DMA_CHAN_INTR_ENA_TIE;
 
        writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
 }
@@ -130,9 +130,9 @@ void dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
        u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
 
        if (rx)
-               value |= DMA_CHAN_INTR_DEFAULT_RX_4_10;
+               value |= DMA_CHAN_INTR_ENA_RIE;
        if (tx)
-               value |= DMA_CHAN_INTR_DEFAULT_TX_4_10;
+               value |= DMA_CHAN_INTR_ENA_TIE;
 
        writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
 }
@@ -144,9 +144,9 @@ void dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
        u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
 
        if (rx)
-               value &= ~DMA_CHAN_INTR_DEFAULT_RX;
+               value &= ~DMA_CHAN_INTR_ENA_RIE;
        if (tx)
-               value &= ~DMA_CHAN_INTR_DEFAULT_TX;
+               value &= ~DMA_CHAN_INTR_ENA_TIE;
 
        writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
 }
@@ -158,9 +158,9 @@ void dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr,
        u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
 
        if (rx)
-               value &= ~DMA_CHAN_INTR_DEFAULT_RX_4_10;
+               value &= ~DMA_CHAN_INTR_ENA_RIE;
        if (tx)
-               value &= ~DMA_CHAN_INTR_DEFAULT_TX_4_10;
+               value &= ~DMA_CHAN_INTR_ENA_TIE;
 
        writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
 }