/* DMA default interrupt mask for 4.00 */
#define DMA_CHAN_INTR_DEFAULT_MASK (DMA_CHAN_INTR_NORMAL | \
DMA_CHAN_INTR_ABNORMAL)
-#define DMA_CHAN_INTR_DEFAULT_RX (DMA_CHAN_INTR_ENA_RIE)
-#define DMA_CHAN_INTR_DEFAULT_TX (DMA_CHAN_INTR_ENA_TIE)
#define DMA_CHAN_INTR_NORMAL_4_10 (DMA_CHAN_INTR_ENA_NIE_4_10 | \
DMA_CHAN_INTR_ENA_RIE | \
/* DMA default interrupt mask for 4.10a */
#define DMA_CHAN_INTR_DEFAULT_MASK_4_10 (DMA_CHAN_INTR_NORMAL_4_10 | \
DMA_CHAN_INTR_ABNORMAL_4_10)
-#define DMA_CHAN_INTR_DEFAULT_RX_4_10 (DMA_CHAN_INTR_ENA_RIE)
-#define DMA_CHAN_INTR_DEFAULT_TX_4_10 (DMA_CHAN_INTR_ENA_TIE)
#define DMA_CHAN_RX_WATCHDOG(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x38)
#define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x3c)
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
if (rx)
- value |= DMA_CHAN_INTR_DEFAULT_RX;
+ value |= DMA_CHAN_INTR_ENA_RIE;
if (tx)
- value |= DMA_CHAN_INTR_DEFAULT_TX;
+ value |= DMA_CHAN_INTR_ENA_TIE;
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
}
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
if (rx)
- value |= DMA_CHAN_INTR_DEFAULT_RX_4_10;
+ value |= DMA_CHAN_INTR_ENA_RIE;
if (tx)
- value |= DMA_CHAN_INTR_DEFAULT_TX_4_10;
+ value |= DMA_CHAN_INTR_ENA_TIE;
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
}
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
if (rx)
- value &= ~DMA_CHAN_INTR_DEFAULT_RX;
+ value &= ~DMA_CHAN_INTR_ENA_RIE;
if (tx)
- value &= ~DMA_CHAN_INTR_DEFAULT_TX;
+ value &= ~DMA_CHAN_INTR_ENA_TIE;
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
}
u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
if (rx)
- value &= ~DMA_CHAN_INTR_DEFAULT_RX_4_10;
+ value &= ~DMA_CHAN_INTR_ENA_RIE;
if (tx)
- value &= ~DMA_CHAN_INTR_DEFAULT_TX_4_10;
+ value &= ~DMA_CHAN_INTR_ENA_TIE;
writel(value, ioaddr + DMA_CHAN_INTR_ENA(dwmac4_addrs, chan));
}