iio: imu: inv-mpu9150: fix irq ack preventing irq storms

IRQ needs to be acked. for some odd reasons, reading from irq status does
not reliable help, enable acking from any register to be on the safe side
and read the irq status register. Comments in the code indicate a known
unreliability with that register.
The blamed commit was tested with mpu6050 in lg,p895 and lg,p880 according
to Tested-bys. But with the MPU9150 in the Epson Moverio BT-200 this leads
to irq storms without properly acking the irq.

Fixes: 0a3b517c8089 ("iio: imu: inv_mpu6050: fix interrupt status read for old buggy chips")
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Acked-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
index b2fa1f4957a5b95892777e6233903ecba4646d70..5796896d54cd86bd154acb68906ee99a55df9a78 100644 (file)
--- a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
+++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c
@@ -1943,6 +1943,14 @@ int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
                        irq_type);
                return -EINVAL;
        }
+
+       /*
+        * Acking interrupts by status register does not work reliably
+        * but seem to work when this bit is set.
+        */
+       if (st->chip_type == INV_MPU9150)
+               st->irq_mask |= INV_MPU6050_INT_RD_CLEAR;
+
        device_set_wakeup_capable(dev, true);
 
        st->vdd_supply = devm_regulator_get(dev, "vdd");

diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
index 211901f8b8eb6fef72e57afabf5cbc3e5140b9b9..6239b1a803f77aba899b9a8ada2305038fd2a840 100644 (file)
--- a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
+++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
@@ -390,6 +390,8 @@ struct inv_mpu6050_state {
 /* enable level triggering */
 #define INV_MPU6050_LATCH_INT_EN       0x20
 #define INV_MPU6050_BIT_BYPASS_EN      0x2
+/* allow acking interrupts by any register read */
+#define INV_MPU6050_INT_RD_CLEAR       0x10
 
 /* Allowed timestamp period jitter in percent */
 #define INV_MPU6050_TS_PERIOD_JITTER   4

diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c
index 10a473342075933a3d485a6e5daa7d5a4d662c07..22c1ce66f99ee583f28e52a91a195f6f4c767013 100644 (file)
--- a/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c
+++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c
@@ -248,7 +248,6 @@ static irqreturn_t inv_mpu6050_interrupt_handle(int irq, void *p)
        switch (st->chip_type) {
        case INV_MPU6000:
        case INV_MPU6050:
-       case INV_MPU9150:
                /*
                 * WoM is not supported and interrupt status read seems to be broken for
                 * some chips. Since data ready is the only interrupt, bypass interrupt
@@ -257,6 +256,10 @@ static irqreturn_t inv_mpu6050_interrupt_handle(int irq, void *p)
                wom_bits = 0;
                int_status = INV_MPU6050_BIT_RAW_DATA_RDY_INT;
                goto data_ready_interrupt;
+       case INV_MPU9150:
+               /* IRQ needs to be acked */
+               wom_bits = 0;
+               break;
        case INV_MPU6500:
        case INV_MPU6515:
        case INV_MPU6880: