zynq: gem: Add support for setup slcr gem clk speed

Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 788a8fd14f54f41a4c906620bdb1183b531d57c4..5a8674ab2cff9b212af75ea43f74c84aa92c404f 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -61,3 +61,29 @@ void zynq_slcr_cpu_reset(void)
 
        writel(1, &slcr_base->pss_rst_ctrl);
 }
+
+/* Setup clk for network */
+void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
+{
+       zynq_slcr_unlock();
+
+       if (gem_id > 1) {
+               printf("Non existing GEM id %d\n", gem_id);
+               goto out;
+       }
+
+       if (gem_id) {
+               /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
+               writel(clk, &slcr_base->gem1_clk_ctrl);
+               /* Configure GEM_RCLK_CTRL */
+               writel(rclk, &slcr_base->gem1_rclk_ctrl);
+       } else {
+               /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
+               writel(clk, &slcr_base->gem0_clk_ctrl);
+               /* Configure GEM_RCLK_CTRL */
+               writel(rclk, &slcr_base->gem0_rclk_ctrl);
+       }
+
+out:
+       zynq_slcr_lock();
+}

diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index d0c69da971f95c74cee43a959f761553cdd51349..2b8fe1a9b213a1be147f36f6e56e88d7b3d9f23c 100644 (file)
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -32,7 +32,12 @@ struct slcr_regs {
        u32 scl; /* 0x0 */
        u32 slcr_lock; /* 0x4 */
        u32 slcr_unlock; /* 0x8 */
-       u32 reserved1[125];
+       u32 reserved0[75];
+       u32 gem0_rclk_ctrl; /* 0x138 */
+       u32 gem1_rclk_ctrl; /* 0x13c */
+       u32 gem0_clk_ctrl; /* 0x140 */
+       u32 gem1_clk_ctrl; /* 0x144 */
+       u32 reserved1[46];
        u32 pss_rst_ctrl; /* 0x200 */
        u32 reserved2[15];
        u32 fpga_rst_ctrl; /* 0x240 */

diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index e78890011a8421be7ccdaad03a831e1e4572d694..57128dc40eccfb4e12436cb6cde51685b86176bc 100644 (file)
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -26,5 +26,6 @@
 extern void zynq_slcr_lock(void);
 extern void zynq_slcr_unlock(void);
 extern void zynq_slcr_cpu_reset(void);
+extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
 
 #endif /* _SYS_PROTO_H_ */

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 8c51d63b8f6e0f7868b424a3af5dd94ca44cea29..bd1c8c095c4f529bade415fe4eee17fd47e90149 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -33,6 +33,7 @@
 #include <phy.h>
 #include <miiphy.h>
 #include <watchdog.h>
+#include <asm/arch/sys_proto.h>
 
 /* Bit/mask specification */
 #define ZYNQ_GEM_PHYMNTNC_OP_MASK      0x40020000 /* operation mask bits */
@@ -357,6 +358,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
        phy_detection(dev);
 
 #ifdef CONFIG_PHYLIB
+       u32 rclk, clk = 0;
+
        /* interface - look at tsec */
        phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
 
@@ -370,29 +373,23 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
        case SPEED_1000:
                writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
                                                                &regs->nwcfg);
-
-               /******* GEM0_CLK Setup *************************/
-               /* SLCR unlock */
-               *(volatile u32 *) 0xF8000008 = 0xDF0D;
-
-               /* Configure GEM0_RCLK_CTRL */
-               *(volatile u32 *) 0xF8000138 = (0 << 4) | (1 << 0);
-
-               /* Set divisors for appropriate frequency in GEM0_CLK_CTRL */
-               *(volatile u32 *) 0xF8000140 = (1 << 20) | (8 << 8) |
-                                               (0 << 4) | (1 << 0);
-
-               /* SLCR lock */
-               *(volatile u32 *) 0xF8000004 = 0x767B;
-
+               rclk = (0 << 4) | (1 << 0);
+               clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
                break;
        case SPEED_100:
                clrsetbits_le32(&regs->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
                        ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
+               rclk = 1 << 0;
+               clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
                break;
        case SPEED_10:
+               rclk = 1 << 0;
+               /* FIXME untested */
+               clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
                break;
        }
+       /* FIXME maybe better to define gem address in hardware.h */
+       zynq_slcr_gem_clk_setup(dev->iobase != 0xE000B000, rclk, clk);
 
 #else
        /* PHY Setup */