re PR target/62098 (incorrect code generated by arm gcc)

Fix PR target/62098

2014-08-12  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/62098
	* config/arm/vfp.md (*combine_vcvtf2i): Fix constraint.
	Remove unnecessary attributes.

From-SVN: r213861

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 23f4327d6259f22697ff8496a34da37f1f136bab..78cc7eaeadfbc4cedeed49bf509d466d2872a6bc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2014-08-12  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+       PR target/62098
+       * config/arm/vfp.md (*combine_vcvtf2i): Fix constraint.
+       Remove unnecessary attributes.
+
 2014-08-12  Yury Gribov  <y.gribov@samsung.com>
 
        * internal-fn.c (init_internal_fns): Fix off-by-one.

diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index ab502ad13c23ca4422bed352d0a0b14ae1fbcf88..005968938f35e16e0650fdbbc8a04a53b881155f 100644 (file)
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1264,17 +1264,15 @@
 )
 
 (define_insn "*combine_vcvtf2i"
-  [(set (match_operand:SI 0 "s_register_operand" "=r")
-       (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t")
+  [(set (match_operand:SI 0 "s_register_operand" "=t")
+       (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "0")
                                 (match_operand 2
                                 "const_double_vcvt_power_of_two" "Dp")))))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math"
-  "vcvt%?.s32.f32\\t%1, %1, %v2\;vmov%?\\t%0, %1"
+  "vcvt%?.s32.f32\\t%0, %1, %v2"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")
-   (set_attr "ce_count" "2")
-   (set_attr "type" "f_cvtf2i")
-   (set_attr "length" "8")]
+   (set_attr "type" "f_cvtf2i")]
  )
 
 ;; Store multiple insn used in function prologue.