amdgcn: Testsuite cond_fmaxnm fixups

These testcases had a typo that means they scan for SFmode twice, and DFmode
never.  They were also incompatible with the pattern names in my address vector
patches (not yet committed).

This patch fixes both issues.

gcc/testsuite/ChangeLog:

	* gcc.target/gcn/cond_fmaxnm_3.c: Fix assembler scan patterns.
	* gcc.target/gcn/cond_fmaxnm_4.c: Fix assembler scan patterns.
	* gcc.target/gcn/cond_fminnm_3.c: Fix assembler scan patterns.
	* gcc.target/gcn/cond_fminnm_4.c: Fix assembler scan patterns.

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
index 5da33ac27267dbf573641d6559c7b115943e70bf..0f1fcfbb149f87229e268d90f638ef48805a7077 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c
@@ -30,8 +30,8 @@
 TEST_ALL (DEF_LOOP)
 
 /* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
-/* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+/* { dg-final { scan-assembler-times {v_cndmask[^\n]*movv64sf} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64df3} 3 } } */
+/* { dg-final { scan-assembler-times {v_mov[^\n]*movv64df[^\n]*exec} 3 } } */
 
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
index 263db35dd499e62f44e06ba5097ef422b8e7d430..7885808bca3d958a4a2cc01176c642149a9b1d94 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c
@@ -30,8 +30,8 @@
 TEST_ALL (DEF_LOOP)
 
 /* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
-/* { dg-final { scan-assembler-times {smaxv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+/* { dg-final { scan-assembler-times {v_cndmask[^\n]*movv64sf} 3 } } */
+/* { dg-final { scan-assembler-times {smaxv64df3} 3 } } */
+/* { dg-final { scan-assembler-times {v_mov[^\n]*movv64df[^\n]*exec} 3 } } */
 
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
index 59bbc5610ced2f08c6f9ab1e4d1b71ed14a8d845..45b63c088147c9ce4415e7c837bc7f2312ae3462 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c
@@ -7,8 +7,8 @@
 #include "cond_fmaxnm_3.c"
 
 /* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
-/* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+/* { dg-final { scan-assembler-times {v_cndmask[^\n]*movv64sf} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64df3} 3 } } */
+/* { dg-final { scan-assembler-times {v_mov[^\n]*movv64df[^\n]*exec} 3 } } */
 
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */

diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
index 07e6aae891977e02b42965e67f1300c6e7d4a3b1..bf41cc615a34486f5159f2b45b5b1067bd766b1d 100644 (file)
--- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
+++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c
@@ -7,8 +7,8 @@
 #include "cond_fmaxnm_4.c"
 
 /* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64sf_exec} 3 } } */
-/* { dg-final { scan-assembler-times {sminv64sf3} 3 } } */
-/* { dg-final { scan-assembler-times {movv64df_exec} 3 } } */
+/* { dg-final { scan-assembler-times {v_cndmask[^\n]*movv64sf} 3 } } */
+/* { dg-final { scan-assembler-times {sminv64df3} 3 } } */
+/* { dg-final { scan-assembler-times {v_mov[^\n]*movv64df[^\n]*exec} 3 } } */
 
-/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-not {\tv_writelane_b32\tv[0-9]+, vcc_..} } } */