reset: th1520: add resets for display pipeline

The VO subsystem of TH1520 contains a few resets for the display
pipeline -- display, MIPI DSI and HDMI controllers.

Add support for them to the reset-th1520 driver.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20250813081716.2181843-3-uwu@icenowy.me
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c
index 7874f0693e1b427a094a68f2b6d783985e789bf8..06e5dff7c524d67208762539e0b0d453ad2f62ee 100644 (file)
--- a/drivers/reset/reset-th1520.c
+++ b/drivers/reset/reset-th1520.c
@@ -14,10 +14,20 @@
  /* register offset in VOSYS_REGMAP */
 #define TH1520_GPU_RST_CFG             0x0
 #define TH1520_GPU_RST_CFG_MASK                GENMASK(1, 0)
+#define TH1520_DPU_RST_CFG             0x4
+#define TH1520_DSI0_RST_CFG            0x8
+#define TH1520_DSI1_RST_CFG            0xc
+#define TH1520_HDMI_RST_CFG            0x14
 
 /* register values */
 #define TH1520_GPU_SW_GPU_RST          BIT(0)
 #define TH1520_GPU_SW_CLKGEN_RST       BIT(1)
+#define TH1520_DPU_SW_DPU_HRST         BIT(0)
+#define TH1520_DPU_SW_DPU_ARST         BIT(1)
+#define TH1520_DPU_SW_DPU_CRST         BIT(2)
+#define TH1520_DSI_SW_DSI_PRST         BIT(0)
+#define TH1520_HDMI_SW_MAIN_RST                BIT(0)
+#define TH1520_HDMI_SW_PRST            BIT(1)
 
 struct th1520_reset_priv {
        struct reset_controller_dev rcdev;
@@ -37,7 +47,35 @@ static const struct th1520_reset_map th1520_resets[] = {
        [TH1520_RESET_ID_GPU_CLKGEN] = {
                .bit = TH1520_GPU_SW_CLKGEN_RST,
                .reg = TH1520_GPU_RST_CFG,
-       }
+       },
+       [TH1520_RESET_ID_DPU_AHB] = {
+               .bit = TH1520_DPU_SW_DPU_HRST,
+               .reg = TH1520_DPU_RST_CFG,
+       },
+       [TH1520_RESET_ID_DPU_AXI] = {
+               .bit = TH1520_DPU_SW_DPU_ARST,
+               .reg = TH1520_DPU_RST_CFG,
+       },
+       [TH1520_RESET_ID_DPU_CORE] = {
+               .bit = TH1520_DPU_SW_DPU_CRST,
+               .reg = TH1520_DPU_RST_CFG,
+       },
+       [TH1520_RESET_ID_DSI0_APB] = {
+               .bit = TH1520_DSI_SW_DSI_PRST,
+               .reg = TH1520_DSI0_RST_CFG,
+       },
+       [TH1520_RESET_ID_DSI1_APB] = {
+               .bit = TH1520_DSI_SW_DSI_PRST,
+               .reg = TH1520_DSI1_RST_CFG,
+       },
+       [TH1520_RESET_ID_HDMI] = {
+               .bit = TH1520_HDMI_SW_MAIN_RST,
+               .reg = TH1520_HDMI_RST_CFG,
+       },
+       [TH1520_RESET_ID_HDMI_APB] = {
+               .bit = TH1520_HDMI_SW_PRST,
+               .reg = TH1520_HDMI_RST_CFG,
+       },
 };
 
 static inline struct th1520_reset_priv *