drm/amdgpu: reorder IB schedule sequence

This reorders the IB schedule sequence to cleanly
separate the vm operation from the IB submission.
This makes the two independent so we can cleanly
associate each one with its respective fence.

v2: fixes for VCN

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 3a7bab87b5d805f55551075269ae2f370efc38a4..bfccb03193d323baa354841272a7cbeb499ae6ee 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -215,16 +215,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
                dma_fence_put(tmp);
        }
 
-       if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
-               ring->funcs->emit_mem_sync(ring);
-
-       if (ring->funcs->emit_wave_limit &&
-           ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
-               ring->funcs->emit_wave_limit(ring, true);
-
-       if (ring->funcs->insert_start)
-               ring->funcs->insert_start(ring);
-
        if (job) {
                r = amdgpu_vm_flush(ring, job, need_pipe_sync);
                if (r) {
@@ -235,6 +225,16 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
 
        amdgpu_ring_ib_begin(ring);
 
+       if (ring->funcs->insert_start)
+               ring->funcs->insert_start(ring);
+
+       if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
+               ring->funcs->emit_mem_sync(ring);
+
+       if (ring->funcs->emit_wave_limit &&
+           ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
+               ring->funcs->emit_wave_limit(ring, true);
+
        if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow)
                amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va,
                                            init_shadow, vmid);
@@ -323,6 +323,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
            ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH)
                ring->funcs->emit_wave_limit(ring, false);
 
+       amdgpu_ring_ib_end(ring);
        /* Save the wptr associated with this fence.
         * This must be last for resets to work properly
         * as we need to save the wptr associated with this
@@ -331,7 +332,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
         */
        amdgpu_fence_save_wptr(af);
 
-       amdgpu_ring_ib_end(ring);
        amdgpu_ring_commit(ring);
 
        return 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 3a5ca6df2fdfa8d9d670f775367b33fd6bada488..83b8a41f559c3fe03c4a1d77a777c1c39f9b7e12 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -815,6 +815,17 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
                return 0;
 
        amdgpu_ring_ib_begin(ring);
+
+       /* There is no matching insert_end for this on purpose for the vm flush.
+        * The IB portion of the submission has both.  Having multiple
+        * insert_start sequences is ok, but you can only have one insert_end
+        * per submission based on the way VCN FW works.  For JPEG
+        * you can as many insert_start and insert_end sequences as you like as
+        * long as the rest of the packets come between start and end sequences.
+        */
+       if (ring->funcs->insert_start)
+               ring->funcs->insert_start(ring);
+
        if (ring->funcs->init_cond_exec)
                patch = amdgpu_ring_init_cond_exec(ring,
                                                   ring->cond_exe_gpu_addr);