aarch64.md (mov<mode>cc): New for GPF.

2014-04-29  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* config/aarch64/aarch64.md (mov<mode>cc): New for GPF.

2014-04-29  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* gcc.target/aarch64/fcsel_1.c: New test case.

From-SVN: r209889

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1799a435274a707d311d380baec27acc5c5a9a6f..9bc2ce05d38d8e1cd477f19ad1a0e45633b1f45a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2014-04-29  Zhenqiang Chen  <zhenqiang.chen@linaro.org>
+
+       * config/aarch64/aarch64.md (mov<mode>cc): New for GPF.
+
 2014-04-28  James Greenhalgh  <james.greenhalgh@arm.com>
 
        * config/aarch64/aarch64-builtins.c

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index a004f9da1c88c73f409a94ca4c1fa794f07dc2fb..266d7873a5a1b8dbb7f955c3f13cf370920a9c4a 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2429,6 +2429,25 @@
   }
 )
 
+(define_expand "mov<mode>cc"
+  [(set (match_operand:GPF 0 "register_operand" "")
+       (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "")
+                         (match_operand:GPF 2 "register_operand" "")
+                         (match_operand:GPF 3 "register_operand" "")))]
+  ""
+  {
+    rtx ccreg;
+    enum rtx_code code = GET_CODE (operands[1]);
+
+    if (code == UNEQ || code == LTGT)
+      FAIL;
+
+    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
+                                 XEXP (operands[1], 1));
+    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+  }
+)
+
 (define_insn "*csinc2<mode>_insn"
   [(set (match_operand:GPI 0 "register_operand" "=r")
         (plus:GPI (match_operator:GPI 2 "aarch64_comparison_operator"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b5a66cec7e9c645430057af6c547edee7bdb0fc1..5fbd76f0b67012a11e6b0e2ac6b32bb4821c1104 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2014-04-29  Zhenqiang Chen  <zhenqiang.chen@linaro.org>
+
+       * gcc.target/aarch64/fcsel_1.c: New test case.
+
 2014-04-28  Jerry DeLisle  <jvdelisle@gcc.gnu>
 
        PR libfortran/60810

diff --git a/gcc/testsuite/gcc.target/aarch64/fcsel_1.c b/gcc/testsuite/gcc.target/aarch64/fcsel_1.c
new file mode 100644 (file)
index 0000000..2704ee0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/fcsel_1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options " -O2 " } */
+
+float
+f_1 (float a, float b, float c, float d)
+{
+  if (a > 0.0)
+    return c;
+  else
+    return 2.0;
+}
+
+double
+f_2 (double a, double b, double c, double d)
+{
+  if (a > b)
+    return c;
+  else
+    return d;
+}
+
+/* { dg-final { scan-assembler-times "\tfcsel" 2 } } */