ARM64: zynqmp: Use the same U-Boot version with/without ATF

Remove SECURE_IOU option which is not needed. U-Boot itself can detect
which EL level it is on and based on that use do platform setup.
It also simplify usage because one Kconfig entry is gone.

Note(from Siva): iou_scntr_secure->base_frequency_id_register
needs to programmed with clock-in value for time stamp counter not the
one hardcoded in the routine(zynqmp_get_system_timer_freq()) above.
This may vary based on psu_init.
Note(from Michal): This is more wider problem because the similar code
is in ATF and this needs to be solved in PCW.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index f47c7377e4c969b62d78386ae5236589c11c8ef6..405781ee0d0fcc3e4772c29835b837a85a323208 100644 (file)
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -40,10 +40,6 @@ config SYS_CONFIG_NAME
        default "xilinx_zynqmp_zc1751_xm016_dc2" if TARGET_ZYNQMP_ZC1751_XM016_DC2
        default "xilinx_zynqmp_zc1751_xm019_dc5" if TARGET_ZYNQMP_ZC1751_XM019_DC5
 
-config SECURE_IOU
-       bool "Configure ZynqMP secure IOU"
-       default n
-
 config ZYNQMP_QSPI
        bool "Configure ZynqMP QSPI"
 

diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c
index 349eb57e8fc1bf14f4c8b16148510c785fe69b2d..690c72dd66836190a5c709900d1d694d8d5fd02d 100644 (file)
--- a/arch/arm/cpu/armv8/zynqmp/clk.c
+++ b/arch/arm/cpu/armv8/zynqmp/clk.c
@@ -28,6 +28,22 @@ unsigned long get_uart_clk(int dev_id)
        return 100000000;
 }
 
+unsigned long zynqmp_get_system_timer_freq(void)
+{
+       u32 ver = zynqmp_get_silicon_version();
+
+       switch (ver) {
+       case ZYNQMP_CSU_VERSION_VELOCE:
+               return 10000;
+       case ZYNQMP_CSU_VERSION_EP108:
+               return 4000000;
+       case ZYNQMP_CSU_VERSION_QEMU:
+               return 50000000;
+       }
+
+       return 100000000;
+}
+
 #ifdef CONFIG_CLOCKS
 /**
  * set_cpu_clk_info() - Initialize clock framework

diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 834fd8ec31d724f61cf914904b7842d87cd8ce36..80019f56369733fd38eb4ffdc2e5dc880fd47989 100644 (file)
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -15,8 +15,23 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static unsigned int zynqmp_get_silicon_version_secure(void)
+{
+       u32 ver;
+
+       ver = readl(&csu_base->version);
+       ver &= ZYNQMP_SILICON_VER_MASK;
+       ver >>= ZYNQMP_SILICON_VER_SHIFT;
+
+       return ver;
+}
+
 unsigned int zynqmp_get_silicon_version(void)
 {
+
+      if (current_el() == 3)
+               return zynqmp_get_silicon_version_secure();
+
        gd->cpu_clk = get_tbclk();
 
        switch (gd->cpu_clk) {

diff --git a/arch/arm/include/asm/arch-zynqmp/clk.h b/arch/arm/include/asm/arch-zynqmp/clk.h
index d55bc31c43993cb7ebbb3fb983e3faecb715b7c7..b18333d1ca25fd29bb13100d58646fe01adb8316 100644 (file)
--- a/arch/arm/include/asm/arch-zynqmp/clk.h
+++ b/arch/arm/include/asm/arch-zynqmp/clk.h
@@ -9,5 +9,6 @@
 #define _ASM_ARCH_CLK_H_
 
 unsigned long get_uart_clk(int dev_id);
+unsigned long zynqmp_get_system_timer_freq(void);
 
 #endif /* _ASM_ARCH_CLK_H_ */

diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 7e22e09cf0939f5f4186b27cd44d606cdb19b613..99d9d3021e835a4e452a967f803bcd60da5a031a 100644 (file)
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -51,11 +51,8 @@ struct crlapb_regs {
 
 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
 
-#if defined(CONFIG_SECURE_IOU)
-#define ZYNQMP_IOU_SCNTR       0xFF260000
-#else
+#define ZYNQMP_IOU_SCNTR_SECURE        0xFF260000
 #define ZYNQMP_IOU_SCNTR       0xFF250000
-#endif
 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN   0x1
 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
 
@@ -67,6 +64,14 @@ struct iou_scntr {
 
 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
 
+struct iou_scntr_secure {
+       u32 counter_control_register;
+       u32 reserved0[7];
+       u32 base_frequency_id_register;
+};
+
+#define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
+
 /* Bootmode setting values */
 #define BOOT_MODES_MASK        0x0000000F
 #define QSPI_MODE_24BIT        0x00000001
@@ -120,9 +125,20 @@ struct apu_regs {
 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
 
 /* Board version value */
+#define ZYNQMP_CSU_BASEADDR            0xFFCA0000
 #define ZYNQMP_CSU_VERSION_SILICON     0x0
 #define ZYNQMP_CSU_VERSION_EP108       0x1
 #define ZYNQMP_CSU_VERSION_VELOCE      0x2
 #define ZYNQMP_CSU_VERSION_QEMU                0x3
 
+#define ZYNQMP_SILICON_VER_MASK                0xF000
+#define ZYNQMP_SILICON_VER_SHIFT       12
+
+struct csu_regs {
+       u32 reserved0[17];
+       u32 version;
+};
+
+#define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
+
 #endif /* _ASM_ARCH_HARDWARE_H */

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 1011339faac48796c9ea6a3208de2df9e8979bfe..6cf9563d720d593e201b8b3ee803342fe4689601 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -11,6 +11,7 @@
 #include <ahci.h>
 #include <scsi.h>
 #include <usb.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
@@ -28,10 +29,18 @@ int board_early_init_r(void)
 {
        u32 val;
 
-       val = readl(&crlapb_base->timestamp_ref_ctrl);
-       val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
-       writel(val, &crlapb_base->timestamp_ref_ctrl);
-
+       if (current_el() == 3) {
+               val = readl(&crlapb_base->timestamp_ref_ctrl);
+               val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+               writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+               /* Program freq register in System counter */
+               writel(zynqmp_get_system_timer_freq(),
+                      &iou_scntr_secure->base_frequency_id_register);
+               /* And enable system counter */
+               writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
+                      &iou_scntr_secure->counter_control_register);
+       }
        /* Program freq register in System counter and enable system counter */
        writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
        writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |

diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig
index b01c6c732193bb9779e44be13aacabde30857e38..1a5fa3061ffecc92989d2b7e63c6f0a1419d20be 100644 (file)
--- a/configs/xilinx_zynqmp_mini_qspi_defconfig
+++ b/configs/xilinx_zynqmp_mini_qspi_defconfig
@@ -1,7 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_TARGET_ZYNQMP_MINI=y
-CONFIG_SECURE_IOU=y
 CONFIG_ZYNQMP_QSPI=y
 CONFIG_SYS_TEXT_BASE=0xFFFC0000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-qspi"